process(rst,clk,cntr)
begin
if(rst = '0') then
cntr <= (others => '0');
elsif(rising_egde(clk)) then
cntr <= cntr + 1;
end if;
end process;
This code is an example of synchronous MOD 2^n counter with clk as clock, rst as asynchronous reset and cntr can be defined as unsigned(n-1 downto 0) in your code declaration.