Configuration specification "all : comp1" applies to no component instantiation statements ERROR

[alizadeharand]

i have this code in VHDL :


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nibble_comparator is
port(a,b : in STD_LOGIC_vector(3 downto 0);
gt,eq,lt: in STD_LOGIC;
a_gt_b, a_eq_b, a_lt_b : out STD_LOGIC);
END nibble_comparator;


ARCHITECTURE iterative2 OF nibble_comparator IS
component comp1
GENERIC(tplh1 : TIME := 2 NS; tplh2 : TIME := 3 NS; tplh3 : TIME := 4 NS;
tphl1 : TIME := 4 NS; tphl2 : TIME := 5 NS; tphl3 : TIME := 6 NS);
port(a,b,gt,eq,lt : in STD_LOGIC;
a_gt_b, a_eq_b,a_lt_b : out STD_LOGIC );
END component;
FOR all: comp1 use entity work.bit_comparator(passed_delay);
CONSTANT n : INTEGER := 4;
signal im : STD_LOGIC_vector(0 to (n-1)*3-1);

BEGIN
c_all: FOR i IN 0 TO n-1 GENERATE
l: IF i = 0 GENERATE
least: comp1 PORT MAP (a(i),b(i),gt,eq,lt,im(0),im(1),im(2));
END GENERATE;
m: IF i = n-1 GENERATE

most: copm1 PORT MAP (a(i),b(i),im(i*3-3),im(i*3-2),im(i*3-1),a_gt_b, a_eq_b,a_lt_b );
END GENERATE;
r: IF i > 0 AND i < n-1 GENERATE
rest: comp1 PORT MAP (a(i),b(i),im(i*3-3),im(i*3-2),im(i*3-1),im(i*3+0),im(i*3+1),im(i*3+2));
END GENERATE;
END GENERATE;
END iterative2;


and i encounter this ERROR:
Configuration specification "all : comp1" applies to no component instantiation statements ERROR