Vhdl code for 4-bit parallel access shift registers

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krisdan

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Please gurus in the house can anyone help me with the code for vhdl code for 4-bit parallel access shift registers and its test bench... Am very new to vhdl and i really need the stuff..waiting for your urgent replies
 

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Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------
ENTITY shiftreg4 IS
PORT ( P: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
       Clock:IN STD_LOGIC;
       LOAD,I:IN STD_LOGIC;
       Q:BUFFER IN STD_LOGIC _VECTOR (3 DOWNTO 0)
      );
END shiftreg4;
------------------------------------------------
ARCHITECTURE arch OF shiftreg4 IS
BEGIN
PROCESS
BEGIN
   WAIT UNTIL Clock'event AND Clock='1';
IF LOAD='1' THEN
Q<=P;
ELSE
Q(0)<=Q(1);
Q(1)<=Q(2);
Q(2)<=Q(3);
Q(3)<=I;
END IF
END PROCESS;
END arch;
------------------------------------------------
 
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