VHDL code correct or incorrect ??

[abhineet22]

Hi i have written one code..is it correct ? if yes then in wave form a and b will synchronizes to clk.because this is sequential modeling ..and waht will be the hardware generated by this code ??

entity g is
port(clk:in std_logic;
a,b ut std_logic);
end g;

architecture behav of g is
begin
process(clk)
begin
if (clk'event and clk ='1')then
a<='1';
b<='1';
else;
a<='0';
b<='0';
end if;
end process;
end behav;

 

[Marcel Majoor]

Let's analyse what your code describes.
The code says: When clk changes (the process becomes active), at a rising edge of the clk (clk'event and clk ='1'), make A/B='1' and in all other cases A/B should be '0'.
You probably want A/B to be '0' at the falling edge.
This is something that can not be done/is not allowed in a single process.

In short, events like this can not have an 'else' clause.

If you want to act on both edges of the clock, then you have to do this in two seperate processes:

  process(clk)
    if rising_edge(clk) then
      ... do something
    end if;
  end process;

  process(clk)
    if falling_edge(clk) then
      ... do something
    end if;
  end process;

The problem with two processes is that they can not both assign to A/B

  process(clk)
    if rising_edge(clk) then
      a <= '1';
      b <= '1';
    end if;
  end process;

  process(clk)
    if falling_edge(clk) then
      a <= '1';         <-- wrong, 'a' can not be assigned in different processes
      b <= '1';         <-- wrong, 'b' can not be assigned in different processes
    end if;
  end process;

What you can do is use additional signals and combine them into the A/B signals.

  ...
  signal a1, b1, a2, b2: std_logic;
  ...
  process(clk)
    if rising_edge(clk) then
      a1 <= '1';
      b1 <= '1';
    end if;
  end process;

  process(clk)
    if falling_edge(clk) then
      a2 <= '0';
      b2 <= '0';
    end if;
  end process;

  a <= a1 or a2;        <-- just some kind of combination for the 'A' signal
  b <= b1 or b2;        <-- just some kind of combination for the 'B' signal

 

[mytechface]

i will suggest

a <= (a1 and clk) or (a2 and not clk);
b <= (b1 and clk) or (b2 and not clk);

just like what i assume a double edged flop will do it.. a mux after the 2 flops.

again, i imagine a1 and b1 always being 1 and a2 b2 always being 0 makes little sense... actually, if this were true, this is implementing a simple buffer ;-)

 

[lucbra]

I'm afraid that after compilation, you will lose some (if not all) of the information you want to reside in your simple equasions.

The solution with 2 processes will work

 

[mytechface]

oh... of course... what i meant was to replace

a <= a1 or a2;
b <= b1 or b2;

with

a <= (a1 and clk) or (a2 and not clk);
b <= (b1 and clk) or (b2 and not clk);

while keeping the rest of the code (the 2 processes) to model double edge flops as the former will not.