May 12, 2009 #1 N n3utr0 Newbie level 1 Joined Mar 17, 2009 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,287 vhdl clock enable Hello, is it possible to affect the same signal in a rising edge and then falling edge of the same clock? for example: if (clock'event and clock='1' and enable='1') then s1 <= 0; end if; if (clock'event and clock='0' and enable='1') then s1 <= 1; end if;
vhdl clock enable Hello, is it possible to affect the same signal in a rising edge and then falling edge of the same clock? for example: if (clock'event and clock='1' and enable='1') then s1 <= 0; end if; if (clock'event and clock='0' and enable='1') then s1 <= 1; end if;
May 12, 2009 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,404 Helped 14,749 Reputation 29,780 Reaction score 14,094 Trophy points 1,393 Location Bochum, Germany Activity points 298,026 vhdl rising edge clock Not in synthesis, cause FFs triggered at both edges don't exist, except in some CPLD families. There are replacements, that utilize two FFs and combinational logic. See a link in in one of the various same topic edaboard threads.
vhdl rising edge clock Not in synthesis, cause FFs triggered at both edges don't exist, except in some CPLD families. There are replacements, that utilize two FFs and combinational logic. See a link in in one of the various same topic edaboard threads.
May 19, 2009 #3 K kvingle Full Member level 5 Joined Nov 5, 2007 Messages 244 Helped 33 Reputation 66 Reaction score 12 Trophy points 1,298 Location India. Activity points 2,574 vhdl rising edge such as coolRunner II CPLD by xilinx