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VHDL - clock rising and falling edge affectation

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n3utr0

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vhdl clock enable

Hello,

is it possible to affect the same signal in a rising edge and then falling edge of the same clock? for example:


if (clock'event and clock='1' and enable='1') then

s1 <= 0;

end if;

if (clock'event and clock='0' and enable='1') then

s1 <= 1;

end if;
 

FvM

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vhdl rising edge clock

Not in synthesis, cause FFs triggered at both edges don't exist, except in some CPLD families. There are replacements, that utilize two FFs and combinational logic. See a link in in one of the various same topic edaboard threads.
 

kvingle

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vhdl rising edge

such as coolRunner II CPLD by xilinx
 

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