n3utr0
Newbie level 1
vhdl clock enable
Hello,
is it possible to affect the same signal in a rising edge and then falling edge of the same clock? for example:
if (clock'event and clock='1' and enable='1') then
s1 <= 0;
end if;
if (clock'event and clock='0' and enable='1') then
s1 <= 1;
end if;
Hello,
is it possible to affect the same signal in a rising edge and then falling edge of the same clock? for example:
if (clock'event and clock='1' and enable='1') then
s1 <= 0;
end if;
if (clock'event and clock='0' and enable='1') then
s1 <= 1;
end if;