-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
USE WORK.ResolutionPkg.ALL;
entity Driver is
port(
CLK : in STD_LOGIC;
InOut_capacitance : inout INTEGER := 0;
Load_capacitance : inout INTEGER := 0
);
end Driver;
architecture Driver of Driver is
---- Component declarations -----
component Fub1
generic(
capacitance : INTEGER := 3
);
port (
CLK : in STD_LOGIC;
InOut_capacitance : inout summing INTEGER;
Load_capacitance : inout summing INTEGER
);
end component;
begin
---- Processes ----
Process_1 :
process (InOut_capacitance, CLK, Load_capacitance)
begin
InOut_capacitance <= summing(InOut_capacitance) + summing(Load_capacitance;)
end process;
end Driver;