[VHDL] Bus resolution function integer from multiple driver

[Ronfante]

Hi all,

I'm searching for a solution to my problem: I've a driver with 3 ports, 2 inout integer and 1 in std_logic, I've to get the data from a bus connected to an unknown number of driver (I've to get the capacitance of each fan-out driver and sum into output).

component Driver
  generic(
       capacitance : INTEGER := 3
  );
  port (
       CLK : in STD_LOGIC;
       Load_capacitance : inout INTEGER;
       InOut_capacitance : inout INTEGER
  );
end component;

I cannot use a tri state buffer because it' doesn't work with integer, so I've found something like that:

FUNCTION wired_and (drivers : MVL_VECTOR) RETURN MVL IS
            VARIABLE accumulate : MVL := '1';
                 BEGIN
                      FOR i IN drivers'RANGE LOOP
                      accumulate := accumulate AND drivers(i);
                      END LOOP;
                 RETURN accumulate;
END wired_and;

But I'm unable to make it work with my driver as I don't know what to pass to the function
and get the capacitance data.

Any suggestion?

Thankyou

 

[K-J]

You have two choices:
- If you keep your top level architecture, then your 'driver' block needs to generate a signal to input into U2 and a separate one for U3 to tell them when they should output their data on the bus.

- Another approach might be to daisy chain the blocks. I notice that 'Driver', 'U2' and 'U3' all have the same interface pins, so I'm guessing they perform the exact same function. If that is the case, then break the connection on your top level between 'Driver' and 'U3' and connect 'U3' up to 'U2' 'InOut_capacitance'. I suspect that this should not really be an 'inout', instead it should be an 'in'. Simillarly, 'Load_capacitance' should probably be an 'out' rather than an 'inout'.

It's not really clear at all why you have these inout ports to begin with. What data are you transferring to and from each one? Your dataflow is not at all defined, what you think is bi-directional even less clear.

Kevin Jennings

 

[Ronfante]

Yes, 'Driver' 'U2' 'U3' have all the same interface.
'Driver' have to get from 'U2' and 'U3' (maybe more 'Ux') their 'capacitance' from 'Load_capacitance' which are integer,
then driver sum his generic capacitance + 'U2 Load_capacitance' + ... 'Ux Load_capacitance',
on the end 'Driver' sent to U2 and U3 on ports 'Load_capacitance' ... Ux that sum

I've used inout ports because 'Driver' have "to know" his fan-out capacitance.

Thank you

 

[FvM]

The design of the"driver" component seems pretty useless, one clock and two inout ports without direction control signals.

Can you write down a table that shows under which condition one or the other port should be driving out?

I don't understand the relation to resolution functions at first sight. They come into play when multiple drivers for a bus exist. But there are no multiple drivers in the scheme.

 

[Ronfante]

First I've used a oe signal and a tri state buffer to menage the inout ports, but with that I can't handle integer.
If needed I can add other ports to the units.
This is a expanded version:

for example:
U12 should output 'Driver capacitance' + 'U2 cap' + 'U3' + 'U4' ... + 'Ux' + 'U12 capacitance'

I've to get for all level all data (the capacitance) from 'Ux' then sent to output.

Thankyou

 

[TrickyDicky]

you cant use integer because it is not a resolved type, but you can use the unsigned or signed types, as they are arrays of std_logic and can easily be converted from integer.

 

[Ronfante]

ok thankyou, so I've to use something like this

USE ieee.numerc_std_unsigned;
....
....
SIGNAL  inc: STD_LOGIC_VECTOR (7 DOWNTO 0);
....
....
inc <= std_logic_vector(to_unsigned(In_capacitance, 8));

in this way I can set the mode of the inout ports,
after I've InOut_capacitance port on read mode I've to receive data from multi-source 'Ux', with tri state buffer I can get 1 input at a time, how can i get all data from 'Ux'?
Can I use a for cycle ?

 

[TrickyDicky]

What is the setup here? are these inside an FPGA? or are you modeling some circuit?
FPGAs cannot have multiple drivers on anything except the physical pins, and then they must be tri-state drivers.

 

[Ronfante]

I'm modeling a circuit, I've only to make logic ports who take data from their fan-out then send the sum to all ports

 

[FvM]

O.K., I finally see what you are trying to achieve. I must confess that it's fairly beyond my scope of synthesizable VHDL.

If it works at all, it must use a resolved signal of the integer or real type with a respective resolution function. I presume it's not exactly forbidden by the VHDL standard, but is it also supported by a simulation tool?

- - - Updated - - -

The VHDL 2008 concept of resolved composite subtypes may be also applied in this case.

 

[Ronfante]

So I'll study composite resolved subtype, thankyou

 

[SynthWorks]

Assuming that this is a behavioral model and not for synthesis, you simply need to write an appropriate resolution function for integers that does the summing:

package ResolutionPkg is 
  function summing  ( s : integer_vector ) return integer ; 
  subtype summing_integer is summing integer ;
end ResolutionPkg ;
package body ResolutionPkg is 
  function summing ( s : integer_vector ) return integer is 
    variable result : integer := 0 ; 
  begin
    for i in s'RANGE loop
      result := result + s(i) ;
    end loop ;
    return result ; 
  end summing ;
end ResolutionPkg ;

You need to make sure each port is actually driving a value (as otherwise it is drivin. One way to do this is make sure there is an explicit assignment done in Driver. Another way to do this is to put an initialization on the port. Note that the use of the subtype that I defined in the package (summing_integer) is optional. In most places, where you can specify a type you can also specify a subtype constraint (such as "summing integer").

component Driver
  generic(
       capacitance : INTEGER := 3
  );
  port (
       CLK : in STD_LOGIC;
       Load_capacitance : inout summing INTEGER := 0 ;
       InOut_capacitance : inout summing INTEGER := 0
  );
end component;

While this is all the language requires, when you rely on port initializations, due to some simulator optimizations (specifically port collapsing), I recommend that you also initialize the signal that connects all of the components together. This may or may not suppress there informational and perhaps confusing messages about port collapsing.

architecture netlist of e is 
  component Driver ... ; 

  signal Load_capacitance : summing integer := 0 ; 
begin 
  
  Driver_1 : Driver ... ; 

   . . .

end netlist;

 

[Ronfante]

hi, thank you for your suggestion, I've tried in this way,

-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
USE WORK.ResolutionPkg.ALL;

entity Driver is
  port(
       CLK : in STD_LOGIC;
       InOut_capacitance : inout INTEGER := 0;
       Load_capacitance : inout INTEGER := 0
  );
end Driver;

architecture Driver of Driver is

---- Component declarations -----

component Fub1
  generic(
       capacitance : INTEGER := 3
  );
  port (
       CLK : in STD_LOGIC;
       InOut_capacitance : inout summing INTEGER;
       Load_capacitance : inout summing INTEGER
  );
end component;

begin

---- Processes ----

Process_1 :
process (InOut_capacitance, CLK, Load_capacitance)
begin
	 InOut_capacitance <= summing(InOut_capacitance) + summing(Load_capacitance;)
end process;

end Driver;

doest it have any sense?