VHDL bit_vector to real

[Mavnus04]

I have a bit_vector(4 downto 0) and I am trying to convert it to a real so that I may write to a file.

dataout <= real(integer(to_signed(std_logic_vector(data)),5));

The error I get is illegal operand for type conversion.

I was able to change real to std_logic_vector:
datain <= std_logic_vector(to_signed(integer(read_data1),4));

So I am not sure what I am missing here. Any help would be great.
Thanks!

- - - Updated - - -

OK. Nevermind.
I was confused on how the functions worked and what they were named.

my solution:
dataout <= real(to_integer(signed(to_stdlogicvector(data))));

 

[TrickyDicky]

I have all sorts of questions:
1. Why are you using bitvector?
2. Why are you converting it to a real? you realise you can write bitvectors to a file?
3. Thats a lot of type conversions - just why?

Did you realise that there is a package called numeric_bit? it does all the same things as numeric_std but using a base type of bit instead of std_logic - it would have saved the std_logic_vector conversion.