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VHDL Basic Input and Output Text File

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VHDLStarter

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Hello, I am trying to read a single line from a text file and then output it to another text file.

Here is my current code:

Code:
library IEEE;
   use IEEE.std_logic_1164.all;
   use ieee.numeric_std.all;
   use Ieee.std_logic_unsigned.all;
   use std.textio.all;

entity tb_project is     
end tb_project;

architecture tb_project_arch of tb_project is
    
begin
  
    
    read_input_file:process
    
      --ouput variables
      variable OUTLINE : LINE;
      file FILEOUT : TEXT is OUT "ouput.TXT";
      --
      --Input variables
			variable inline:line;
			variable character_variable:character; --should this be a string?
			variable end_of_line:boolean;
			file myfile:text is "input.txt";
			
	begin
	  
		while not endfile(myfile) loop
			readline(myfile,inline);
			read(inline,character_variable,end_of_line);
			--end_of_line is EOLN boolean flag
			while end_of_line loop
				read(inline,character_variable,end_of_line);
				WRITE(OUTLINE,character_variable); --add variable to outline variable for output.
			end loop;
	end loop;
	   WRITELINE(FILEOUT, OUTLINE); --writes outline variable to file.
	
	wait;	--Do nothing when finished
	end process read_input_file;
end tb_project_arch;
I have a text file that has "abcd" in it. However, after I simulate it my output.txt file reads "bcdd".

I have had trouble finding a basic example of inputting and outputting. I used this code here: "Reading an input file via VHDL" tutorial

My questions are:

1- Am inputting the line correctly? Do I have the right type of variable for what I want to do?

2- Do I have the output statements in the right position? As I previously stated, the output is not in the proper order.

3- I am interested in trying to use a string and call to specific bits instead of a character. Is this possible?

Thanks.
 

TrickyDicky

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1. yes. It is fine. The problem you have is because you call the read function before the loop, therefore pulling the a off the line and moving stright to b for output. The double d occurs becuase you loop until the d char is reached, but end_of_line is true (I think you've got your variable name wrong) until it cannot read any more chars from the line. in this case, nothing is written to character_variable and so d is written again.

2. See my answer to 1.

3. the quick answer is yes, you can read any basic types from a text file (character, bit, bit_vector, real, integer) and there is another package that allows you to read/write std_logic_vectors directly to text files (ieee.std_logic_textio). So you can just do this:

variable my_int : integer;

...
read(inline, my_int);

Basically text file IO is quite well covered in VHDL. and you can do plenty of useful things with it. What is not well defined is binary file IO.
 

VHDLStarter

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The problem you have is because you call the read function before the loop
Thanks for the reply, but I am having trouble implementing what you suggested in step 1. There are two loops. a while not and a while loop inside of the while not loop. I see a read call in both of these loops. However, I do not see a read call before the while not loop starts. There is just a begin before the while loop.


Code:
[B]begin[/B]

[B]while not endfile(myfile) loop[/B]
			readline(myfile,inline);
			read(inline,character_variable,end_of_line);
			--end_of_line is EOLN boolean flag
			[B]while end_of_line loop[/B]
				read(inline,character_variable,end_of_line);
				WRITE(OUTLINE,character_variable); --add variable to outline variable for output.
			[B]end loop;[/B]
	[B]end loop;[/B]
	   WRITELINE(FILEOUT, OUTLINE); --writes outline variable to file.
Can you please clarify what you suggested in order to fix the problem? What should I specifically move and where? Thanks.
 

TrickyDicky

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heres the fix:

Code:
while not endfile(myfile) loop
  readline(myfile,inline);
  --end_of_line is EOLN boolean flag

  end_of_line := true;

  while end_of_line loop
    read(inline,character_variable,end_of_line);
    WRITE(OUTLINE,character_variable); --add variable to outline variable for output.
  end loop;
end loop;
 

VHDLStarter

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Thanks for the reply. I used the code you have provided and that fixed the ordering issue. However, the output still has an extra d. It outputs "abcdd" instead of just "abcd". Is it possible to fix this?

Code:
while not endfile(myfile) loop
       readline(myfile,inline);
        --end_of_line is EOLN boolean flag
        end_of_line := true;
       while end_of_line loop
          read(inline,character_variable,end_of_line);
          WRITE(OUTLINE,character_variable); --add variable to outline variable for output.
        end loop;
      end loop;

WRITELINE(FILEOUT, OUTLINE); --writes outline variable to file.
 

TrickyDicky

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The last d is because you write a character even if there is no more characters on the line.

try this:

Code:
while not endfile(myfile) loop
       readline(myfile,inline);
        --end_of_line is EOLN boolean flag
        end_of_line := true;
       while end_of_line loop
          read(inline,character_variable,end_of_line);
          if end_of_line then --you need to rename your variables to be more meaningful
            WRITE(OUTLINE,character_variable); --add variable to outline variable for output.
          end if;
        end loop;
      end loop;

WRITELINE(FILEOUT, OUTLINE); --writes outline variable to file.
 

VHDLStarter

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Nice, that worked perfectly! Thank you so much once again. You have really helped me a lot. I really appreciate it.
 

VHDLStarter

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Thanks for the reply. I am currently having an issue converting the code to string representation. Currently I have:

Code:
variable string1 : string(1 to 80) := (others => ' ');		
			
	begin

while not endfile(myfile) loop
       readline(myfile,inline);
        --end_of_line is EOLN boolean flag
        end_of_line := true;
        read(inline,string1,end_of_line);
       while end_of_line loop
           read(inline,string1,end_of_line);
          if end_of_line then --you need to rename your variables to be more meaningful
            WRITE(OUTLINE,string1); --add variable to outline variable for output.
          end if;
        end loop;
      end loop;


WRITELINE(FILEOUT, OUTLINE); --writes outline variable to file.
Unfortunately, I keep getting a blank text document in the output. I checked out the resource you provided and it helped a bit, but I am still stuck. Can you try to correct my implementation?

edit:

I found this example:

VHDL Verification Course

Here is my code:

Code:
library IEEE;
   use IEEE.std_logic_1164.all;
   use ieee.numeric_std.all;
   use Ieee.std_logic_unsigned.all;
   use std.textio.all;
   

entity tb_project is     
end tb_project;

architecture tb_project_arch of tb_project is
    
begin
  
    
    read_input_file:process
    
      --ouput variables
      variable OUTLINE : LINE;
      file FILEOUT : TEXT is OUT "ouput.TXT";
      --Input variables
			variable inline:line;
			variable character_variable:character; 
			variable end_of_line:boolean;
			file myfile:text is "input.txt";
			--other read variables
			variable int1 : integer;
			variable string1 : string(1 to 80) := (others => ' ');
			variable in_string: boolean;
			
			
	begin
	  
--main portion of code starts here!

    readline(myfile, OUTLINE);
     -- clear the contents of the result string
     for i in string1'range loop
         string1(i) := ' ';
     end loop;   
     -- read all characters of the line, up to the length  
     -- of the results string
     for i in string1'range loop
        read(OUTLINE, character_variable, in_string);
        string1(i) := character_variable;
        if not in_string then -- found end of line
           exit;
        end if;   
     end loop; 
    
      
      if (string1(1 to 4) = "abcd")then
        WRITE(OUTLINE,string'("hi "));
      else
        WRITE(OUTLINE,string'(" hello"));
      end if;
      
      write(OUTLINE,string1);

WRITELINE(FILEOUT, OUTLINE); --writes outline variable to file.

	


	wait;	--Do nothing when finished
	end process read_input_file;
end tb_project_arch;
I have the same problem I had before in a previous post. Basically it adds an extra character at the end. Instead of printing out "Hi abcd" it prints out "hi abcdd".
 
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TrickyDicky

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its the same problem as before. You are putting the extra "d" on because you are not exiting the loop before you append the char to the string. So "d" is still in character_variable after it goes over the end of the line. in_string is only "true" after there are no more characters left on the line.
 

VHDLStarter

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its the same problem as before. You are putting the extra "d" on because you are not exiting the loop before you append the char to the string. So "d" is still in character_variable after it goes over the end of the line. in_string is only "true" after there are no more characters left on the line.
You are correct. I apologize, but I am having a bit of trouble implementing your suggestion. The code is a bit different from before, but it seems to be the same principle. You will notice that there is no while loop anymore, instead there is a for loop because I am using a modified example from the source I previously mentioned in my other post. Here is the specific part of my code after the string is cleared to read from the file:

Code:
  for i in string1'range loop
        read(OUTLINE, character_variable, in_string);
        string1(i) := character_variable;
        if not in_string then -- found end of line
           exit;
        end if;   
     end loop;
I am a bit confused for the adjustment. If you could show me, that would be greatly appreciated. Thank you.
 
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TrickyDicky

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Modified, very similar to before.

Code:
for i in string1'range loop
  read(OUTLINE, character_variable, in_string);  
  if in_string then -- found end of line
      string1(i) := character_variable;
  else
     exit;
  end if;   
end loop;
 

73FRI

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Asking for help..
i need help for FPGA xylink spartan 3A with VHDL language

my project is to connect PS2 keyboard to xylinx spartan 3 (XC3S700AN)

would u like to give me some simple examples about my project :eek:

btw i use Xilinx ISE Design Suite 12.4 :D

sorry for this noob question :eek:
 

mrflibble

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Second step - Don't cut and paste the exact same question across 5 threads. One will do just fine.
 

VHDLStarter

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Modified, very similar to before.

Code:
for i in string1'range loop
  read(OUTLINE, character_variable, in_string);  
  if in_string then -- found end of line
      string1(i) := character_variable;
  else
     exit;
  end if;   
end loop;
Thank you so much for helping me. This really helped. I think I am able to finish my project. Thanks again.
 

73FRI

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