muss76
Newbie level 4
Hi
I am using an array pixel_mem for storing pixel data. But I am asked to use Block ram instantiation. So I have tried to understand how to implement BRAM instantiation template in place of array named pixel_mem of type ram_array.
Here is the code segment which I am using:
-------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY filter IS
GENERIC( window_size : INTEGER :=3; -- Size of Kernel/Window
d_width : INTEGER :=8; -- Size of each Pixel
depth : INTEGER :=256; -- Number of pixels in a row
rows : INTEGER :=256 -- Number of Rows in Image file
);
PORT( Clk_50MHz : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Read_flag : IN STD_LOGIC;
Write_flag : OUT STD_LOGIC;
Data_in : IN SIGNED(d_width-1 + 1 DOWNTO 0); -- Pixel Data as Signed (binary)
Data_out : OUT SIGNED(d_width-1 + 1 DOWNTO 0)
);
END filter;
-- Define an architecture for the filter entity.
architecture structural of filter is
-- Array of Coefficients for Convolution (Binary form)
SIGNAL window_coef_reg : SIGNED(window_size*window_size*(d_width + 1) - 1 downto 0);
-- Memory to hold Rows for Convolution
type ram_array is array (INTEGER RANGE 0 to window_size-2, INTEGER RANGE 0 to depth-1) of
SIGNED(d_width-1 + 1 downto 0);
SIGNAL pixel_mem: ram_array;
-----------------------------------------------------------------------------------------
Actually I am unable to understand how to used template for Instantiating BRAM to hold pixel data that is being stored in signal pixel_mem. I have some templates like:
-- RAMB16_S9 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAMB16_S9_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
Library UNISIM;
use UNISIM.vcomponents.all;
-- <-----Cut code below this line and paste into the architecture body---->
-- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
-- Spartan-3
-- Xilinx HDL Language Template, version 12.3
RAMB16_S9_inst : RAMB16_S9
generic map (
INIT => X"000", -- Value of output RAM registers at startup
SRVAL => X"000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the initial contents of the RAM
-- Address 0 to 511
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
........
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
I
.........
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
.......
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
.......
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 511
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => DO, -- 8-bit Data Output
DOP => DOP, -- 1-bit parity Output
ADDR => ADDR, -- 11-bit Address Input
CLK => CLK, -- Clock
DI => DI, -- 8-bit Data Input
DIP => DIP, -- 1-bit parity Input
EN => EN, -- RAM Enable Input
SSR => SSR, -- Synchronous Set/Reset Input
WE => WE -- Write Enable Input
);
-- End of RAMB16_S9_inst instantiation
Please anyone there to help me.
Best regards
I am using an array pixel_mem for storing pixel data. But I am asked to use Block ram instantiation. So I have tried to understand how to implement BRAM instantiation template in place of array named pixel_mem of type ram_array.
Here is the code segment which I am using:
-------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY filter IS
GENERIC( window_size : INTEGER :=3; -- Size of Kernel/Window
d_width : INTEGER :=8; -- Size of each Pixel
depth : INTEGER :=256; -- Number of pixels in a row
rows : INTEGER :=256 -- Number of Rows in Image file
);
PORT( Clk_50MHz : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Read_flag : IN STD_LOGIC;
Write_flag : OUT STD_LOGIC;
Data_in : IN SIGNED(d_width-1 + 1 DOWNTO 0); -- Pixel Data as Signed (binary)
Data_out : OUT SIGNED(d_width-1 + 1 DOWNTO 0)
);
END filter;
-- Define an architecture for the filter entity.
architecture structural of filter is
-- Array of Coefficients for Convolution (Binary form)
SIGNAL window_coef_reg : SIGNED(window_size*window_size*(d_width + 1) - 1 downto 0);
-- Memory to hold Rows for Convolution
type ram_array is array (INTEGER RANGE 0 to window_size-2, INTEGER RANGE 0 to depth-1) of
SIGNED(d_width-1 + 1 downto 0);
SIGNAL pixel_mem: ram_array;
-----------------------------------------------------------------------------------------
Actually I am unable to understand how to used template for Instantiating BRAM to hold pixel data that is being stored in signal pixel_mem. I have some templates like:
-- RAMB16_S9 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAMB16_S9_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
Library UNISIM;
use UNISIM.vcomponents.all;
-- <-----Cut code below this line and paste into the architecture body---->
-- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
-- Spartan-3
-- Xilinx HDL Language Template, version 12.3
RAMB16_S9_inst : RAMB16_S9
generic map (
INIT => X"000", -- Value of output RAM registers at startup
SRVAL => X"000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the initial contents of the RAM
-- Address 0 to 511
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
........
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
I
.........
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
.......
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
.......
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 511
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => DO, -- 8-bit Data Output
DOP => DOP, -- 1-bit parity Output
ADDR => ADDR, -- 11-bit Address Input
CLK => CLK, -- Clock
DI => DI, -- 8-bit Data Input
DIP => DIP, -- 1-bit parity Input
EN => EN, -- RAM Enable Input
SSR => SSR, -- Synchronous Set/Reset Input
WE => WE -- Write Enable Input
);
-- End of RAMB16_S9_inst instantiation
Please anyone there to help me.
Best regards