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VHDL Block ram instantiation

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May 26, 2010
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I am using an array pixel_mem for storing pixel data. But I am asked to use Block ram instantiation. So I have tried to understand how to implement BRAM instantiation template in place of array named pixel_mem of type ram_array.

Here is the code segment which I am using:



ENTITY filter IS
GENERIC( window_size : INTEGER :=3; -- Size of Kernel/Window
d_width : INTEGER :=8; -- Size of each Pixel
depth : INTEGER :=256; -- Number of pixels in a row
rows : INTEGER :=256 -- Number of Rows in Image file

Read_flag : IN STD_LOGIC;
Write_flag : OUT STD_LOGIC;
Data_in : IN SIGNED(d_width-1 + 1 DOWNTO 0); -- Pixel Data as Signed (binary)
Data_out : OUT SIGNED(d_width-1 + 1 DOWNTO 0)
END filter;

-- Define an architecture for the filter entity.
architecture structural of filter is

-- Array of Coefficients for Convolution (Binary form)
SIGNAL window_coef_reg : SIGNED(window_size*window_size*(d_width + 1) - 1 downto 0);

-- Memory to hold Rows for Convolution
type ram_array is array (INTEGER RANGE 0 to window_size-2, INTEGER RANGE 0 to depth-1) of
SIGNED(d_width-1 + 1 downto 0);

SIGNAL pixel_mem: ram_array;

Actually I am unable to understand how to used template for Instantiating BRAM to hold pixel data that is being stored in signal pixel_mem. I have some templates like:
-- RAMB16_S9 : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (RAMB16_S9_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : reference and connect this function to the design.
-- : All inputs and outputs must be connected.

-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
-- Spartan-3
-- Xilinx HDL Language Template, version 12.3

RAMB16_S9_inst : RAMB16_S9
generic map (
INIT => X"000", -- Value of output RAM registers at startup
SRVAL => X"000", -- Ouput value upon SSR assertion
-- The following INIT_xx declarations specify the initial contents of the RAM
-- Address 0 to 511
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",

INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 511
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 1023
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1024 to 1535
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 1536 to 2047
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => DO, -- 8-bit Data Output
DOP => DOP, -- 1-bit parity Output
ADDR => ADDR, -- 11-bit Address Input
CLK => CLK, -- Clock
DI => DI, -- 8-bit Data Input
DIP => DIP, -- 1-bit parity Input
EN => EN, -- RAM Enable Input
SSR => SSR, -- Synchronous Set/Reset Input
WE => WE -- Write Enable Input

-- End of RAMB16_S9_inst instantiation

Please anyone there to help me.

Best regards


I would use COREGEN and create block ram module 8Bit x 65,536 (16 bit address) with parity bit. You could use lower 8bit address for row and higher 8bit address for column (pixels).


Dear v

Thank you for your suggestion. Unfortunately I am asked to use instantiating technique. Any help in that direction, plz...

If what you have is really a ram, does it really need to be initialised? If you are relying on initialised data in the ram, are you sure you dont want a rom instead?

Do you have any specific questions about instantiating ram/rom? or do you just not understand the process at all? VHDL allows you to write structural elements as well as behavioural elements. What you're talking about here is a behavioural model from which XST can infer a BRAM.If you stray from the template, XST may not be able to see it as a ram, and will not place a BRAM. Below is the basic template for a synchronous single clock dual port ram:

type ram_type is array(0 to 2**n-1) of std_logic_vector(7 downto 0);
  --feel free to replace std_logic_vector with pretty much any other type.
  signal my_ram  : ram_type;

    if rising_edge(clk)
      if wr_en = '1' then
        my_ram(wr_addr)   <= input;
      end if;
      --Use this if you have a registered data output
      output            <= my_ram(rd_addr);
      --Use this if the read address is registered and read data is asynchronous
      --read_addr_r       <= rd_addr;
    end if;
  end process;
  --Use this if the read address is registered and read data is asynchronous
  --output            <= my_ram(read_addr_r);

Hi TrickyDicky

Many thanks for your reply.

Yes I need help with use of INSTANTIATION mthod for Block RAM and not behavioral or Core gen techniques.
Although there are some templates available in template library for INSTANTIATION of block ram, but unfortunately I am unable to understand how to use them in my code. Kindly can you help me in that, I really need help in this regard

You are getting confused.

instantiation would require the use of cre-gen or direct instantiation of a library block (basically what core-gen does)
Behavioural allows XST to infer a BRAM from behavioural code, like the code you posted in your first post.

So which is it?

Dear TrickyDicky

Again thank you.
Initially I used following array for infering block ram:

type ram_array is array (INTEGER RANGE 0 to window_size-2, INTEGER RANGE 0 to depth-1) of
SIGNED(d_width-1 + 1 downto 0);

SIGNAL pixel_mem: ram_array;

as you mentioned other way for creating block ram are core gen and bram instantiation.
So I need help in replacing this array with instantiation. Although I have found many snippets for instantiation but unfortunately I am unable to use these snippets. please help me.

if you are instantiating, I would highly recommend using core-gen. I am not familiar with Xilinx libraries, but there should be help somewhere on how to set up all of the parameters.

basically, when instantiating a BRAM:

some_bram : bram
generic map (
  parameter_1 => X,
  parameter_2 => Y,
port map (
  clk => clk,
  reset => reset,
  addr => addr,

To instantiate you do not need the typeing you did (type ram_array etc). That is behavioural and not instantiration.

have you read any of Xilinx's documentation? They have several examples.

does the existing design synthesize to BRAMs?

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