VHDL assign statement error

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karvin89

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Hi,
The following statement does not parse.

Code: 
 RGB_OUT_local <= video_ram(conv_integer(conv_integer(vecHcount_640_60)+(176*conv_integer(vecVcount_640_60))))
	
							when ((vecHcount_640_60 < 176) && (vecVcount_640_60 < 144)) else (others => '0');


I found that when I remove one of the conditions, it works.

Code: 
 RGB_OUT_local <= video_ram(conv_integer(conv_integer(vecHcount_640_60)+(176*conv_integer(vecVcount_640_60))))
	
							when (vecHcount_640_60 < 176)  else (others => '0');


But I need to check for both vecHcount_640_60 and vecVcount_640_60. Is there anyway I could do this? I am new to VHDL.



Regards,

Karthik
 

try this


Code: 
if  (vecHcount_640_60 < 176) then
      if(vecVcount_640_60 < 144) then 
                RGB_OUT_local <= video_ram(conv_integer(conv_integer(vecHcount_640_60)+(176*conv_integer(vecVcount_640_60)))) 
      end if;
else
      (others => '0'); 
end if;
let me know if it doesn't work
 

When writing VHDL, you should follow VHDL syntax and use VHDL operators...
&& isn't a VHDL defined operator. VHDL says AND.
 

I tried FvM's suggestion and used "AND" and it worked. I am new to VHDL and crossing over from Verilog.

I wonder if mo.khairy.mo's tip, will work outside the process () block. Its a 25 min compile so haven't tried it yet. But thanks anyway guys.
 

A VHDL quick reference clarifies, that it can't work.

To test syntax details, you don't need to compile a full design.
 

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