verilog testbench books
Hi Keith,
Aim of testbench is to verify the functionality of Device Under Test (DUT), so you need to generate the various possible inputs for DUT and observe the outputs of DUT. One way to make sure that DUT is behaving correctly is to compare the output with the expected output for the inputs provided to DUT. You can use behavioural model off DUT for generating expected outputs.
You can instantiate the DUT in your testbench and drive its inputs from testbench.
You can refer to books for detailed description. If you have some specific doubt, do post it.
Regards,
Jitendra