[SOLVED] VHDL and Verilog difference

[Mina Magdy]

could any one told me what is the different between (Variable in VHDL and reg in Verilog ) and (Signal in VHDL and wire in Verilog)

 

[TrickyDicky]

The things you mention are not comparable. You might as well ask whats the difference between an integer in C and the letter 'E'

Variables in VHDL similar to blocking assignments in verilog
Signals are like non-blocking in verilog