VHDL-AMS: reference current

[swordfish01]

Hi,

I'm having a problem writing a VHDL-AMS model for a current sink. I have a working model for a sink that can be turned on / turned off. Now I want to expand that model by a reference input to make it more like a current controlled current source that can be turned off. How can I make this kind of reference input?

I tried having a terminal, defining a current through the reference terminal and a ground terminal but with this approach I would also have to provide a equation for i_ref:

library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;

architecture vhdlams of curr_sink is
  quantity v across i through p_t to n_t;
  quantity v_ref across i through ref_t to n_t;
begin
  if enable_i = '1' use
    i == i_ref;
  else
    i == 0.0;
  end use;
end vhdlams;

Any hints how I can realize behaviour like this?
Basically I just want to "measure" the current going through two ports...

Regars,
Andreas

Edit: I forgot to say that I can get it to work by e.g. providing some "input resistance" at the reference terminal (v_ref == i_ref * 1.0, but is there a way of having the block there without having an impedance?