VHDL-AMS question about behavior model and hold stage

[safwatonline]

VHDL-AMS

i am kind of new in VHDL-AMS and i am trying to make a simple behavior model of a sample and hold stage using VHDL-AMS, it should act on the positive edge of the pin "clk" then capture the voltage of a pin "vin" into an output electrical terminal pin "vout".
the thing is i made an "if-use" statement to detect the positive edge of the signal clk, and then i put the statement "vout==vin", but this seems not to work as the compiler needs to have another condition "if-else" statement on "vout,vin". can anyone help here!
regards,
Safwat

 

[safwatonline]

VHDL-AMS

does anyone know a vhdl-ams forum?

 

[ree]

Re: VHDL-AMS

can u please tell me what's the tool you are using? and how i can get it?
thanks a lot

 

[safwatonline]

VHDL-AMS

i am using Mentor Flow using Design architect for test bench and ADMS as the simulator