VHDL "after" statement

[carbon9]

vhdl after statement

Hi,

I'm trying to use "after" statement to change some variables as the time passes as in the following code:

library ieee;
use ieee.std_logic_1164.all;

entity p82 is

   port(a, c, clk, rst: in std_logic;
       x: out std_logic);
end p82;

architecture behavior of p82 is
      
type state is (stateA, stateB);
signal pr_state, nx_state: state;

begin

-----Lower Section--------

   process(rst, clk)
   begin
      if(rst='1') then
         pr_state<=stateA;
      elsif(clk'event and clk='1') then
         pr_state<=nx_state;
      end if;
   end process;

---Upper Section----------

   process(a, c, pr_state)
   begin
      
      case pr_state is
         
         when stateA =>
            x<='1' after 10 ns;
            x<='0' after 20 ns ;
            nx_state<=stateB;
                     
         when stateB =>
            x<='0' after 10 ns;
            x<='1' after 20 ns;
            nx_state<=stateA;
      
      end case;
   
   end process;

end behavior;

I simulate this design in Multisim. I use a 100 ns clock. When the machine is in stateA, according to the code, x must be logic 1 at t=10ns and the go to logic 0 at t=20ns. But in the simulations, x becomes logic 0 at t=20ns only. I can not see it in logic 1 between t=10ns and t=20ns. How can I solve this?

Regards

 

[vomit]

after statement vhdl

It has to do with the delay model. A full explanation is too long to write here, read it at http://www.gmvhdl.com/delay.htm or **broken link removed**, http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm

Basically, in the default VHDL inertial delay, your second "slower" signal assignment statement cancels the future update of the first.

You could schedule multiple updates in one statement to correct this

            x<='1' after 10 ns, '0' after 20 ns;

 

[shnain]

after statement in vhdl

or write it in another fashion :

...

when stateA => 
            wait for 10 ns;
              x<='1' ;
            wait for  20 ns;
              x<='0' ; 
            nx_state<=stateB; 

...

Yours,
Said.

 

[vomit]

after statements in vhdl

...

when stateA => 
            wait for 10 ns;
              x<='1' ;
            wait for  20 ns;
              x<='0' ; 
            nx_state<=stateB; 
...

The process has a sensitivity list, so it's forbidden to use 'wait' statements. Also, waiting would block the process so it can't respond to other input signals that might change.

 

[carbon9]

vhdl

Thanks for replies. I've tried to increase thenumber of states and the problem is now solved.

Regards

 

[govandi999]

why use after statement in vhdl

give the full code here

 

[eject]

after * 1 ns vhdl

Some VHDL tool will not do this delay as i know.

 

[sridharjubliant]

use wait statement ............. sure u will get output....