[SOLVED] VHDL 4 digit 7-segment display on nexys 3 board

[jianhuachews]

Hi guys i've had all my codes done but when i download the program to my board, the four 7-segment shows the same number (lets say i press 3). It wasn't what i intended. i want it to be like when i press a 123 it first shows 1 in the first segment, then 1 in the second segment while 2 in the first segment, and finally 1 in the third segment while 2 in the second segment while 3 in the first segment (shifting).

Can anyone look at my codes and guide me along? of cus i have my top lvl and crystal code all done but i think it's this 3 program that affects the unexpected behavior instead..

thanks in adv!

keypad decoder

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity key_decode is
port ( 
        key_out : out std_logic_vector(15 downto 0);
        enable1 : out std_logic;
        row_indata, column_in : in std_logic_vector(3 downto 0);
        clk1, rst1 : in std_logic
        );
end key_decode;

architecture Behavioral of key_decode is
signal key_data: std_logic_vector(3 downto 0);
signal key_out_s: std_logic_vector(15 downto 0);
signal key_detect: std_logic;
begin
  
enable1 <= '0' when row_indata = "1111" else 
            '1';
            
process(clk1)
begin
			if (rst1 = '1') then
				key_out_s <= (others => '0');
				key_detect <= '0';
			elsif(clk1'event and clk1 ='1') then
				if (key_detect = '1') then
					key_out_s(15 downto 4) <= key_out_s(11 downto 0);
					key_out_s(3 downto 0) <= key_data;
					key_detect <= '0';
				end if;
				
				
           if(row_indata="0111" and column_in="0111") then
                key_data<="0001";  -- binary for 1
					 key_detect <= '1';
           elsif(row_indata="0111" and column_in="1011") then
                key_data<="0010"; -- binary for 2
					 key_detect <= '1';
           elsif(row_indata="0111" and column_in="1101") then
                key_data<="0011"; -- binary for 3
					 key_detect <= '1';
           elsif(row_indata="0111" and column_in="1110") then
                key_data<="1111"; -- binary for F
					 key_detect <= '1';
           elsif(row_indata="1011" and column_in="0111") then
                key_data<="0100"; -- binary for 4
					 key_detect <= '1';
           elsif(row_indata="1011" and column_in="1011") then
                key_data<="0101"; -- binary for 5
					 key_detect <= '1';
           elsif(row_indata="1011" and column_in="1101") then
                key_data<="0110"; -- binary for 6
					 key_detect <= '1';
           elsif(row_indata="1011" and column_in="1110") then
                key_data<="1110"; -- binary for E
					 key_detect <= '1';
           elsif(row_indata="1101" and column_in="0111") then
                key_data<="0111"; -- binary for 7
					 key_detect <= '1';
           elsif(row_indata="1101" and column_in="1011") then
                key_data<="1000"; -- binary for 8		 
					 key_detect <= '1';
           elsif(row_indata="1101" and column_in="1101") then
                key_data<="1001"; -- binary for 9
					 key_detect <= '1';
           elsif(row_indata="1101" and column_in="1110") then
                key_data<="1101"; -- binary for D
					 key_detect <= '1';
           elsif(row_indata="1110" and column_in="0111") then
                key_data<="1010"; -- binary for A
					 key_detect <= '1';
           elsif(row_indata="1110" and column_in="1011") then
                key_data<="0000"; -- binary for 0
					 key_detect <= '1';
           elsif(row_indata="1110" and column_in="1101") then
                key_data<="1011"; -- binary for B
					 key_detect <= '1';
           elsif(row_indata="1110" and column_in="1110") then
                key_data<="1100"; -- binary for C  
					 key_detect <= '1';
           end if;
        end if;
end process;

key_out <= key_out_s;

end Behavioral;

7segment

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity segment7 is
port ( 
        seg_out : out std_logic_vector(6 downto 0);
        mux_in : in std_logic_vector(3 downto 0)
        );
end segment7;

architecture Behavioral of segment7 is
begin
  
seg_out <= "1000000" when mux_in="0000" else
           "1111001" when mux_in="0001" else
           "0100100" when mux_in="0010" else
           "0110000" when mux_in="0011" else
           "0011001" when mux_in="0100" else
           "0010010" when mux_in="0101" else
           "0000010" when mux_in="0110" else
           "1111000" when mux_in="0111" else
           "0000000" when mux_in="1000" else
           "0011000" when mux_in="1001" else
           "0001000" when mux_in="1010" else
           "0000011" when mux_in="1011" else
           "1000110" when mux_in="1100" else
           "0100001" when mux_in="1101" else
           "0000110" when mux_in="1110" else
           "0001110";
end Behavioral;

mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux is
port ( 
        mux_out : out std_logic_vector(3 downto 0);
        key_in : in std_logic_vector(15 downto 0); 
        mux_g : in std_logic_vector(3 downto 0);
        clk,rst2 : in std_logic
);
end mux;

architecture Behavioral of mux is
signal firstseg: std_logic_vector(3 downto 0);
signal secondseg: std_logic_vector(3 downto 0);
signal thirdseg: std_logic_vector(3 downto 0);
signal fourthseg: std_logic_vector(3 downto 0);

begin

firstseg <= key_in(3 downto 0); --G1<=mux_g(0), first 
secondseg <= key_in(7 downto 4);
thirdseg <= key_in(11 downto 8);
fourthseg <= key_in(15 downto 12);

process(clk)
begin
			if (rst2 = '1') then
				mux_out <= (others => '0');
  elsif(clk'event and clk='1') then
      if(mux_g="1110") then
        mux_out<=firstseg;
      elsif(mux_g="1101") then
        mux_out<=secondseg;
      elsif(mux_g="1011") then
        mux_out<=thirdseg;
      elsif(mux_g="0111") then
        mux_out<=fourthseg;
      end if;
    end if;
end process;
end Behavioral;

 

[treqer]

the upper level is not enough