library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.all;
entity counter_32 is
port(
CLK, IN_SET : in std_logic;
IN_RESET : in std_logic;
IN_UP : in std_logic;
IN_DOWN : in std_logic;
OUT_COUNT: out std_ulogic_vector (31 downto 0)
);
end counter_32;
architecture arc_counter_32 of counter_32 is
signal temp_count: std_ulogic_vector (31 downto 0):= (others=>'0');
begin
sync_process: process (CLK, IN_RESET)
variable counter : std_ulogic_vector (31 downto 0);
begin
if (IN_RESET='1') then
counter := (others=>'0');
elsif (rising_edge(CLK)) then
--counter := counter+1;
if (IN_UP) then
temp_count <= temp_count +1;
elsif (IN_DOWN) then
temp_count <= temp_count - 1;
end if;
end if;
OUT_COUNT <= counter;
end process;
end arc_counter_32;