VHDL 32 bit up/down counter

[graphene]

Hallo,

I am trying to implement a 32-bit up/down counter in VHDL.I am using Xilinx ISE and I get errors which I am not understanding despite searching the internet.
I am also unable to find a pro-code in the internet.
Help and suggestions needed. Thank you in advance.

The errors are

ERROR:HDLCompiler:1731 - "\\file\home$\narayanan\ISE work directory\JGD_counter.vhd" Line 28: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:HDLCompiler:1731 - "\\file\home$\narayanan\ISE work directory\J_counter.vhd" Line 30: found '0' definitions of operator "-", cannot determine exact overloaded matching definition for "-"
ERROR:HDLCompiler:1728 - "\\file\home$\narayanan\ISE work directory\J_counter.vhd" Line 29: Type error near in_down ; current type std_logic; expected type boolean
ERROR:HDLCompiler:1728 - "\\file\home$\narayanan\ISE work directory\J_counter.vhd" Line 27: Type error near in_up ; current type std_logic; expected type boolean
ERROR:HDLCompiler:854 - "\\file\home$\narayanan\ISE work directory\J_counter.vhd" Line 16: Unit <arc_counter_32> ignored due to previous errors.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.all;

entity counter_32 is
port(
	CLK, IN_SET	: in std_logic;
	IN_RESET : in std_logic;
	IN_UP : in std_logic;
	IN_DOWN : in std_logic;
	OUT_COUNT: out std_ulogic_vector (31 downto 0)
	);
end counter_32;

architecture arc_counter_32 of counter_32 is

signal temp_count: std_ulogic_vector (31 downto 0):= (others=>'0');
begin
	sync_process: process (CLK, IN_RESET)
		variable counter : std_ulogic_vector (31 downto 0);
		begin
		if (IN_RESET='1') then
			counter := (others=>'0');
		elsif (rising_edge(CLK)) then
			--counter := counter+1;
			if (IN_UP) then
			temp_count <= temp_count +1;
			elsif (IN_DOWN) then
			temp_count <= temp_count - 1;
			end if;
		end if;
OUT_COUNT <= counter;
		end process;
	

end arc_counter_32;

 

[TrickyDicky]

well, the main problem is you havent included an arithmatic library that does arithmatic with std_ulogic_vector. There is no standard library that can do this.

For a VHDL standard way of doing it, you need to used the unsigned type. Std_logic_vector or std_ulogic was not intended to be a numerical representation of a number- just a collection of Bits. the unsigned and signed types from numeric_std allow this by declaring arrays of std_logic that then represent the number representation you want.

so for your design, delete std_logic_arith (it clashes with numeric_std and is non-standard) change the std_ulogic_vector to unssigned and it should work as intended.

The following code modifies your existing code to do this and fixes your other syntax errors:

---

Code VHDL - [expand]
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library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity counter_32 is
port(
    CLK, IN_SET : in std_logic;
    IN_RESET : in std_logic;
    IN_UP : in std_logic;
    IN_DOWN : in std_logic;
    OUT_COUNT: out unsigned (31 downto 0)
    );
end counter_32;
 
architecture arc_counter_32 of counter_32 is
 
signal temp_count: unsigned (31 downto 0):= (others=>'0');
begin
    sync_process: process (CLK, IN_RESET)
        begin
            if (IN_RESET='1') then
                temp_count <= (others=>'0');
            elsif (rising_edge(CLK)) then
                --counter := counter+1;
                if IN_UP = '1' then
                    temp_count <= temp_count +1;
                elsif IN_DOWN = '1' then
                    temp_count <= temp_count - 1;
                end if;
            end if;
        end process;
    
 
    OUT_COUNT <= temp_count
    
end arc_counter_32;

---

 

[graphene]

First of all thank you Tricky,,,

Sorry, I had tried including library as well. I earlier removed that to avoid conflict..

and just a minute before tried the same once again.. no go.. also the code you gave is getting synthesised with errors

 

[axcdd]

just add ";" after

OUT_COUNT <= temp_count

 

[graphene]

thankyou axcdd.. but I corrected this ; error before posting this (but used my first written code in the forum)....
.
this error is something different...
and now I tried the code with jsut the area of error where it pints out for the definition of operator,,, "+ and -"
.
here are the erros for the code below.
.
.
ERROR:HDLCompiler:1731 - "\\file\home$\narayanan\ISE work directory\Counter_32\per_trial.vhd" Line 53: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
ERROR:HDLCompiler:1731 - "\\file\home$\narayanan\ISE work directory\Counter_32\per_trial.vhd" Line 55: found '0' definitions of operator "-", cannot determine exact overloaded matching definition for "-"
ERROR:HDLCompiler:854 - "\\file\home$\narayanan\ISE work directory\Counter_32\per_trial.vhd" Line 46: Unit <behavioral> ignored due to previous errors.

..
.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity per_trial is
	port(
		CLK, IN_SET	: in std_logic;
		IN_RESET 	: in std_logic;
		IN_UP 		: in std_logic;
		IN_DOWN 		: in std_logic;
		OUT_COUNT	: out std_ulogic_vector (31 downto 0)
		);
end per_trial;

 
architecture Behavioral of per_trial is [B]-- LINE 46[/B]

	signal temp_count: std_ulogic_vector  (31 downto 0):= (others=>'0');
begin
    sync_process: process (IN_UP, IN_DOWN)
        begin
                if (IN_UP = '1') then
                    temp_count <= temp_count +1; [B]--- LINE 53[/B]
                elsif (IN_DOWN = '1') then
                    temp_count <= temp_count - 1;[B] -- LINE 55[/B]
					 else 
						temp_count <= (others=>'0');
                end if;
         end process;
end Behavioral;

 

[TrickyDicky]

Your new post has exactly the same problems I posted before: std_ulogic_vector has NO arithmetic functions. You will have to write your own.

But what is wrong with the code I posted?