rourabpaul
Member level 3
I am using ise14.1 vhdl
I have a record
and types
I declared 2 signals
now I want a slice of buffer_7 into buffer_n which is giving array index error when I wrote this line
I have a record
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 type t_ChargeProperties is record Charge : t_Charge; --10 Time : t_Time;--10 Row : t_Row;--6 Pad : t_Pad;--8 --Gain : t_Gain;--13 --Branch : t_Branch;--1 FLPad : std_logic;--1 end record;
and types
Code VHDL - [expand] 1 2 3 type t_ChargeProperties_stream is array ( 0 to 7) of t_ChargeProperties; type t_ChargeProperties_stream_n is array ( 0 to 3) of t_ChargeProperties; type t_ChargeProperties_stream_7 is array ( 0 to 8 ) of t_ChargeProperties_stream;
I declared 2 signals
Code VHDL - [expand] 1 2 signal buffer_7 : t_ChargeProperties_stream_7; signal buffer_n : t_ChargeProperties_stream_n;
now I want a slice of buffer_7 into buffer_n which is giving array index error when I wrote this line
Code VHDL - [expand] 1 buffer_n<=buffer_7(0)(0 to 3);