Its all a question of bandwidth. If you're using a frame buffer, a single sram, and your pixel clock is 50Mhz, then you can write at this speed, but you'll never have enough time to read it again, which would be pretty uselss. To solve this you need to double the bandwidth. Either you double the clock or more (so you can get twice as much data into or out of the ram) or double the number of rams (meaning you have another interface). With this second one, you can use a swing buffer approach so as you're writing to one memory you read from the other, so you never get any contention.
With a single SRAM, you will probably need some form of FIFO or buffer (a line delay you talk about) to ensure you avoid contention. Because, like you say, you have a 2 clock delay for a read, you'll probably want to read an entire line at a time to make sure you're not constantly holding up the memory access switching from reads to writes. Like mrflibble said - its only a pipeline delay, so if you read a whole line at a time, you're only "waiting" for 2 clocks. If you keep swapping from reading to writing, you're waiting 2 clocks for every read, wasting a lot of time accessing the memory. So because you're reading a whole line, you need to buffer a whole line at the write side. So when the write buffer is getting full, you can dump it to memory (remember its running at 2x input speed so you'll empty it faster than it can fill).