Very simple question about VHDL language

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lahrach

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Hi friends,

what is the difference betwenn these two statements;

1- std_logic;
2- std_logic_vector(0 downto 0);

I found this in Core Generator when creating a BRAM

regards;
 

A type definition isn't a statement, by the way.

A parameterizable component that expects port signals of the std_logic_vector type must be connected to signals of the second kind, if you want them one bit wide, e.g. a RAM with 1 bit data width. You can't use std_logic in this case, but you can assign it to std_logic and vice versa in your code.
 

1 is a normal type, 2 is an array type of std_logic.

So forget the fact that on a synthesised board, they would be the same thing, we're in the VHDL strong type world.

So, heres some code with comments:

Code: 
signal a : std_logic;
signal b : std_logic_vector(0 downto 0);

a <= b; --illegal because b is an array and a isnt
b <= a; --illegal opposite of above

a <= b(0); --legal - because element 0 is a std_logic
b(0) <= a; --legal - because a is a std_logic being connected to element 0 of the array

FvM - and you are correct about the ram - I messed around once with quartus creating an array of std_logic to try and infer a ram - it didnt like it. I raised a support request (and knowing altera, it dissapeared into the ether)
 
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