verilos (Xilinx ISE) XST:2634 For loop stop condition ...

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verilog (Xilinx ISE) XST:2634 For loop stop condition ...

Hi,
I've got some errors by synthesize a verilog code. I've googled this errors but I couldn't find a solution. Can someone help me ? For the code block below,

/*8by8'lik alt bloklarin uyum toplamlari elde ediliyor*/
reg [0:6*4-1] sum_8by8_q; //There are four 8by8 sub blocks
reg [0:6*2-1] array_1D_sum_8by8 [0:1]; //2 rows
reg [5:0] array_2D_sum_8by8 [0:1][0:1]; //2 rows, 2 columns

always@(posedge clk) begin
for(i=5'd0;i<5'd2;i=i+1'b1) begin:computation_of_2D_array_sum_8by8_row
for(j=5'd0;j<5'd2;j=j+1'b1) begin:computation_of_array_sum_8by8_column
array_2D_sum_8by8[j <=array_2D_sum_4by8[2*i][j]+array_2D_sum_4by8[2*i+1][j]+pixels_4by4_15_q[2*i][2*j+1][2];
end
end
end

always@* begin
for(i=5'd0;i<5'd2;i=i+1'b1) begin:computation_of_1D_array_sum_8by8_row
array_1D_sum_8by8 = {array_2D_sum_8by8[0],array_2D_sum_8by8[1]};
end
end
always@(posedge clk) begin
sum_8by8_q <= {array_1D_sum_8by8[0],array_1D_sum_8by8[1]};
end



I've got this errors,
ERROR:Xst:2634 - "../hdl_files/255_to_8_vbsme_parallel_counter.v" line 137: For loop stop condition should depend on loop variable or be static.
ERROR:Xst:1468 - "../hdl_files/255_to_8_vbsme_parallel_counter.v" line 144: Unexpected event in always block sensitivity list.