Verilog

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-- OR gate
-- two descriptions provided

library ieee;
use ieee.std_logic_1164.all;
entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;
architecture OR_arch of OR_ent is
begin

process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;

end OR_arch;

architecture OR_beh of OR_ent is
begin

F <= x or y;
end OR_beh;
why we have to mention the "architecture OR_beh of OR_ent is " Architecture for that one is already defined above & why we have to mention the Process statement here.
 

Let me clarify u in this way..

1.In c language all the statements compiled or executed only after the main statement, similarly in the same way all the instructions execute under "process" block.


2. You have to control the controller to identify the entity block, so you define a architecture name of ENTITY block.
Entity is just defining the inputs and outputs but architecture tells the behavior of the entity mentioned.

If you are not convinced, reply me soon.:smile:
 

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