I have to write a verilog code combining structural and behavioural statements. But i need to execute these structural code at every clock cycle. Can i write these Strustural statemnets inside the always block???? otherwise hw do i do it?? a quick reply ll be a lot of help...
I think all loops that can be easely written out unrolled are synthesisable. For doing this, think as a preprocessor that will unroll the loop, substituting the loop variable, and there you go...
For(i=0,i< 10,i++)
I think this works.....
where as this......
For(i=0,i<k,i++)
where k is a variable.........changes during simulation.....
I dont think it will be synthesisable........
One way to overcome this would be to have multiple for loops iterating at fixed values of 1,2,4,8,16..etc which are sequential in nature
if for eg you wanted to iterate the loop for k= 13 times
k = 00001101;
you can use these bits to appropriate enable a loop as in
connect k[0] to loop iterating 1 time
connect k[2] to loop iterating 4 times
connect k[3] to loop iterating 8 times
For some reason the follow Verilog code does not work correctly in Quartus II 10.0. I am trying to write a function that set all bits to the right of the most significant set bit:
Code:
function [31:0] mask (input [31:0] tap);
integer index;
mask = tap;
for (index = 1; index < 32; index = index * 2) begin
mask = mask | (mask >> index);
end
endfunction
The code synthesizes as if the different iterations of the for loop are concurrent.
Any explanation appreciated.
What I want to do is simple. Given any input word I want to return a word with 1's in all positions right of the leftmost 1. For example, given
32b'00000001000000000000000000000000
I want
32b'00000001111111111111111111111111
Or given
32b'00010100101001010101001010010011
I want
32b'00011111111111111111111111111111
The loop should do this, since it uses a blocking assignment. Starting with
32b'00000001000000000000000000000000
after each iteration I should get
32b'00000000110000000000000000000000 // index == 1
32b'00000000111100000000000000000000 // index == 2
32b'00000000111111110000000000000000 // index == 4
32b'00000000111111111111111100000000 // index == 8
32b'00000000111111111111111111111111 // index == 16
thanks for the reply jducluzeau, but if it doesn't work in a function, why would it work in a module? Besides there are other interconnect problems when using a module. With a function, each module that uses it can have it's own copy.
I was actually going to suggest the exact opposite -- that your original code used mask = mask | (tap >> index); instead of mask = mask | (mask >> index);
even then, I don't see where you get the output you get. for example, i'd expect a pattern of 11101000100000001 as a result of a 1 being shifted 0, 1, 2, 4, 8 times. It seems to be shifting tap by 1,2,4,8 times then or-ing the result.
You might make an intermediate variable to see if this helps.
Personally, I wouldn't do it with for loop. Sometimes for loop helps for readability, but yours isn't very clear at a first glance. I'd rather go with case statements for a better readability unless it requires 100's of lines.
For loop is synthesisable if it runs for a constant time..You can think of a hardware in which what happens if your code executes for one time, and then its replicas will be synthesized after using for loop.... Remember, anything dynamic is not synthesized..The thing is that can we visualize the scenario thats it..
The correct statement is mask = mask | (mask >> index);
I dumped the result of this function out to the 7-segment LED on the dev board and verified that index*2 and index+1 actually produce the same correct results now. I'm not sure what happened to the original bug.
I decided to use a function written like jducluzeau's with a for loop, not a generate loop. This is works and is understandable.
Code:
function [31:0] mask (input [31:0] tap);
integer index;
mask[31] = tap[31];
for (index = 30; index >= 0; index = index - 1) begin
mask[index] = tap[index] | mask[index + 1];
end
endfunction