verilog .. warning problem.

Iam getting the following warning in simulation:
# ** Warning: (vsim-3015) F:/verilog/up_down.vl(7): [PCDPC] - Port size (1 or 1) does not match connection size (3) for port 'count'.

Code is as Follows:


//up_down counter
module main_module(data,up_down,load,reset,enable,clock,count);
input[2] data;
input up_down,load,reset,enable;
inout clock;
output[2] count;
clock_gen i2(clock);
up_down i1 (data,up_down,load,reset,enable,clock,count);
endmodule


module up_down(data,up_down,load,reset,enable,clock,count);
input[2] data;
input up_down,load,reset,enable,clock;
output[2] count;
reg count;
always @(posedge clock or reset)
begin
if(reset) count <=3'b000;
else
if(enable)
begin
if(load) count<=data;
else
begin
if(up_down) count<= count+1;
else count<= count -1;
end
end
end
endmodule


module clock_gen(clock);
output clock;
reg clock;
initial
begin
clock =1;
forever
begin
#50 clock = 0;
#50 clock = 1;
end
end
endmodule

Added after 1 hours 7 minutes:

prob solved..

reg count; --> reg[2:0] count;

yes, the input data should be modified!