process(Input)
variable rCount : std_logic_vector(log2(Input'length) downto 0);
begin
rCount := (others=>'0');
for i in 0 to Input'length-1 loop
if Input(i)='1' then
rCount := Count+'1';
end if;
end loop;
Count <= rCount;
end process;
Count = $countones(Input);
int count, rcount;
always_comb begin
count = 0;
for(int i=$low(Input);i<=$high(Input);i++)
count += Input[i];
rcount = count;
end
reg [15:0] Input;
always @(Input) begin
count =0;
for(i=0;i<16;i=i+1);
count = count + Input[i];
rcount = count;
end
If you can use SystemVerilog, then it is simply
Count = $countones(Input);
If this needs to be synthesizable and your tool does not accept this,
then try
int count, rcount;
always_comb begin
count = 0;
for(int i=$low(Input);i<=$high(Input);i++)
count += Input;
rcount = count;
end
If this is Verilog, then you have to write it knowing how Input was declared, or assuming a max size
reg [15:0] Input;
always @(Input) begin
count =0;
for(i=0;i<16;i=i+1);
count = count + Input;
rcount = count;
end
variable rCount : std_logic_vector(log2(Input'length) downto 0);
module(.....);
parameter x = 16;
input [x-1 : 0] inp;
integer count =0;
integer i;
..
..
..
...
always@(inp)
begin
count = 0;
for(i =0; i < x; i =i+1)
if(inp[i]) count = count + 1;
//Here it will implement latch since we do not give else statement, but I guess this is what we want.
end
//count is the number of one's you want
endmodule
The Verilog equivalent of the VHDL code example must use blocking assignments.Also from my readings till now i did not find any use for the blocking assignment and i found it not recommended. Is using blocking assignment here a must ? And will the synthesizable code will behave the same as the VHDL code ?
The logic calculating the number of ones will be always combinational, even if you register the result. I presume that you don't consider to count the ones in a sequential state machine, one clock cycle per bit. That would be possible of course, but pretty useless. For very wide bit vectors or fast clocked designs, breaking the bit count into multiple pipelined parts may be appropriate.But don't you think you should be implementing your system in synchronous manner, this way it quite simple (and I think you have made things complicated, I don't know VHDL much, what to the extent I know I think it is complicated, the thing could have been much simple)
module tb;
parameter x = 32; //or any other value
//function calling
reg[3:0] temp = logar2(x);
//function declaration
//LOG2 function
function [3:0] logar2;
input [7:0] x;
reg[3:0] var = 0;
begin
while( x != 0 )
begin
x = x/2;
var = var + 1;
end
logar2 = var-1;
end
endfunction
variable rCount : std_logic_vector(log2(Input'length) downto 0);
input [x-1 : 0] inp; //where x is constant parameter, if it is changing quntity, you will get error
Referring to the original VHDL code, it seems clear that the vector length is constant. Otherwise the VHDL code won't work.the length of vector should be constant
Referring to the original VHDL code, it seems clear that the vector length is constant. Otherwise the VHDL code won't work.
variable rCount : std_logic_vector(log2(Input'length) downto 0);
If log2 is supported in VHDL synthesis then ok, it could be constant, but for verilog since one has to make function or task to get log2 value, hence in my opinion taking log2 as the port width is not possible, if you know some different method of doing so, please share.
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