verilog - VHDL variables

[eng.amr2009]

I have this code to count number of ones in a std_logic_vector in VHDL

process(Input)
  variable rCount : std_logic_vector(log2(Input'length) downto 0);
begin
  rCount := (others=>'0');
  for i in 0 to Input'length-1 loop
    if Input(i)='1' then
      rCount := Count+'1';
    end if;
  end loop;
  Count <= rCount;
end process;

I need to know how to implement this code in verilog ? I'm somehow new to verilog.
Thanks in advance.

 

[dave_59]

If you can use SystemVerilog, then it is simply

Count = $countones(Input);

If this needs to be synthesizable and your tool does not accept this,
then try

int count, rcount;
always_comb begin
   count = 0;
     for(int i=$low(Input);i<=$high(Input);i++)
     count += Input[i];
   rcount = count;
   end

If this is Verilog, then you have to write it knowing how Input was declared, or assuming a max size

reg [15:0] Input;
always @(Input) begin
   count =0;
   for(i=0;i<16;i=i+1);
      count = count + Input[i];
  rcount = count;
  end

 

[eng.amr2009]

If you can use SystemVerilog, then it is simply

Count = $countones(Input);

If this needs to be synthesizable and your tool does not accept this,
then try

int count, rcount;
always_comb begin
count = 0;
for(int i=$low(Input);i<=$high(Input);i++)
count += Input;
rcount = count;
end

If this is Verilog, then you have to write it knowing how Input was declared, or assuming a max size

reg [15:0] Input;
always @(Input) begin
count =0;
for(i=0;i<16;i=i+1);
count = count + Input;
rcount = count;
end

Yes I need it to be synthesizable verilog (not system verilog) code.
In your verilog code, you assumed the count is the variable in which you accumulate number of ones and then you assign the accumulated count into the rcount assuming rcount is the output of the module ?
Also from my readings till now i did not find any use for the blocking assignment and i found it not recommended. Is using blocking assignment here a must ? And will the synthesizable code will behave the same as the VHDL code ?

Thanks in advance

 

[syedshan]

Dear

variable rCount : std_logic_vector(log2(Input'length) downto 0);

Well to my knowledge you cannot declare the registers or signals in verilog with variable like this, you have to give constant length of vector and since the log2() function is not synthesizable in verilog you cannot even use that.

Any ways why need the log2 of the vector length??

But don't you think you should be implementing your system in synchronous manner, this way it quite simple (and I think you have made things complicated, I don't know VHDL much, what to the extent I know I think it is complicated, the thing could have been much simple)

well in verilog combinational design it would go like this

module(.....);
parameter x = 16;
input [x-1 : 0] inp;

integer count =0;
integer i;
..
..
..
...
always@(inp)
begin
count = 0;
for(i =0; i < x; i =i+1) 
    if(inp[i]) count = count + 1;
//Here it will implement latch since we do not give else statement, but I guess this is what we want.
end

//count is the number of one's you want

endmodule

Again I should say you should check and implement the design in synchronous fashion.
I hope this helps.

Bests,
Shan

 

[FvM]

Also from my readings till now i did not find any use for the blocking assignment and i found it not recommended. Is using blocking assignment here a must ? And will the synthesizable code will behave the same as the VHDL code ?

The Verilog equivalent of the VHDL code example must use blocking assignments.

But don't you think you should be implementing your system in synchronous manner, this way it quite simple (and I think you have made things complicated, I don't know VHDL much, what to the extent I know I think it is complicated, the thing could have been much simple)

The logic calculating the number of ones will be always combinational, even if you register the result. I presume that you don't consider to count the ones in a sequential state machine, one clock cycle per bit. That would be possible of course, but pretty useless. For very wide bit vectors or fast clocked designs, breaking the bit count into multiple pipelined parts may be appropriate.

 

[syedshan]

Hi

FvM

Thank you for correction . Yes you are right, no need to waste clock cycles...


Thanks
Shan

 

[eng.amr2009]

Yes. as FvM said, i need to calculate it combinationally. The vectors are not that long to result in a long combinational path.
The log2 function is implemented in a VHDL package. Can implement it in a verilog package and include it ?

 

[syedshan]

To implement in verilog you can make the function like the following I have posted below

Are you familiar with functions in verilog.

module tb;

parameter x = 32; //or any other value

//function calling
reg[3:0] temp = logar2(x);

//function declaration
//LOG2 function
function [3:0] logar2;
	input [7:0] x;
	reg[3:0] var = 0;
begin
	while( x != 0 )
	begin
		x = x/2;
		var = var + 1;
	end
	logar2 = var-1;
end
endfunction

endmodule

any ways, you cannot give the variable bit length to any signal in verilog.
Bests,
Shan

 

[eng.amr2009]

I can't get your point about variable length. The vector'length in VHDL is a built in facility that gets the length of the vector. The vector length is surely fixed, either defined by numbers like [63:0] or as a function of a parameter length = 64 and the vector is defined as [(length-1):0]

 

[syedshan]

variable rCount : std_logic_vector(log2(Input'length) downto 0);

Neither log2, not 'length is possible in verilog, for that you have to use:

1) function for log2
2) parametrized value for inp port (input is the reserved word in verilog)

the length of vector should be constant like,

input [x-1 : 0] inp; //where x is constant parameter, if it is changing quntity, you will get error

Bests,
Shan

 

[FvM]

the length of vector should be constant

Referring to the original VHDL code, it seems clear that the vector length is constant. Otherwise the VHDL code won't work.

 

[syedshan]

Referring to the original VHDL code, it seems clear that the vector length is constant. Otherwise the VHDL code won't work.

Yes of course, but referring to log2 in following

variable rCount : std_logic_vector(log2(Input'length) downto 0);

If log2 is supported in VHDL synthesis then ok, it could be constant, but for verilog since one has to make function or task to get log2 value, hence in my opinion taking log2 as the port width is not possible, if you know some different method of doing so, please share.


Bests,
Shan

 

[prady019]

can't we use a std_logic_vector(value downto 0), were value is greater then we need and we take values as

x ((value-3) downto 0) <= y ( value downto 0); -- rest of bit's will go to overflow

like :-

a <= d(msb downto X);
b <= d(X-1 downto Y);
c <= d(Y-1 downto 0);

 

[FvM]

If log2 is supported in VHDL synthesis then ok, it could be constant, but for verilog since one has to make function or task to get log2 value, hence in my opinion taking log2 as the port width is not possible, if you know some different method of doing so, please share.

I'm not sure about the options in Verilog. In VHDL we are often using functions to calculate constants, or in other words to perform compile time calculations. The function isn't actually synthesized, the constant result is used e.g. to initialize a signal or define a vector length. I assume that the same should be possible in Verilog, but I'm not using Verilog that intensively.