Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

verilog, verilog-A and verilog-AMS

Status
Not open for further replies.

hmsheng

Full Member level 4
Joined
Dec 17, 2003
Messages
219
Helped
26
Reputation
52
Reaction score
10
Trophy points
1,298
Location
China
Activity points
1,556
what's the difference of verilog, verilog-A and verilog-AMS?
 

verilog is for digital design.
the other two are the behavior language for analog model.
 

verilog is used for to describe digital circuits and is sensitive to only logic level 1 & logic level 0. verilog _A & verilog_AMS used to describe analog circuits & is sensitive to analog signals.
 

verilog ==> log language such as c++

Verilog-A Verilog-AMS ==> describes analoge behavior such as resistor,cap,inductor or opamp
 

Verilog(Verilog-D): one of two major HDL for Digital
Verilog-a : Language for Analog behavior modeling
Verilog-AMS : Language for Analog Mixed Signal System
 

verilog--for digital
verilogA---for analog
verilog AMS----for mixed signal
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top