verilog transport delay in non-blocking and blocking assignment

[onion2014]

What is the difference between the following lines of code ?
reg1<= #10 reg2 ;
reg3 = # 10 reg4 ;

can anyone explain the difference, from the view of verilog event queue? Thanks.

 

[dave_59]

Two are differences: the non-blocking assignment does block the process the statement is in; the blocking assignment - blocks. The blocking assignment schedules an update of the LHS as soon as the statement completes, and the non-blocking assignment always schedules the update of the LHS at some time after the statement completes.

If you had the follwoing code, and assuming reg1 was 1 and reg2 was 2:

begin 
  $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2);
  reg1 = #10 reg2 ;
  reg2 = #10 reg1 ; 
  $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
end

The first display statement would show the values 1 and 2, and 20 time units later the second $display statement would show the values 2 and 2. That is because the update to reg1 happens at time+10 before the second assignment statement executes.

If you had

begin 
  $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2);
  reg1 <= #10 reg2 ;
  reg2 <= #10 reg1 ; 
  $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
  #10 $display("Display3 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
  #1 $display("Display4 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
end

The first two display statements would always display the same values for reg1 and reg2 at the same time regardless of the delay (the old values), and thew would both display in order at the same time. The third display statement will also the old values, but 10 time units later. The updates to the LHS occur after all the other things scheduled for that time slot have executed. The 4th display statement will display the updated values, 2 and 1.

There is no good reason to use the blocking assignment with a delay.

 

[onion2014]

for this expression --> reg3 = # 10 reg4 ;
does verilog evaluate the RHS immediate and after that 10 time unit, the reg3 is updated? This sounds wired..., it's a blocking assignment...
how about #10 reg3 = reg4;
does verilog just schedule the update in 10 time unit and then at that moment, verilog read reg4 and update reg3? This will cancel the active event queue in time queue, right?


I have a new piece of code in the same topic and simulation result, my question is why cc is alway 'X'


thanks in advance

Two are differences: the non-blocking assignment does block the process the statement is in; the blocking assignment - blocks. The blocking assignment schedules an update of the LHS as soon as the statement completes, and the non-blocking assignment always schedules the update of the LHS at some time after the statement completes.

If you had the follwoing code, and assuming reg1 was 1 and reg2 was 2:

begin 
  $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2);
  reg1 = #10 reg2 ;
  reg2 = #10 reg1 ; 
  $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
end

The first display statement would show the values 1 and 2, and 20 time units later the second $display statement would show the values 2 and 2. That is because the update to reg1 happens at time+10 before the second assignment statement executes.

If you had

begin 
  $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2);
  reg1 <= #10 reg2 ;
  reg2 <= #10 reg1 ; 
  $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
  #10 $display("Display3 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
  #1 $display("Display4 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
end

The first two display statements would always display the same values for reg1 and reg2 at the same time regardless of the delay (the old values), and thew would both display in order at the same time. The third display statement will also the old values, but 10 time units later. The updates to the LHS occur after all the other things scheduled for that time slot have executed. The 4th display statement will display the updated values, 2 and 1.

There is no good reason to use the blocking assignment with a delay.

 

[dave_59]

For

reg3 = # 10 reg4 ;
next_statement;

The right hand side is evaluated at the current time, then the assignment statement waits 10 time units. then makes an assignment to the left hand side, reg3. The next_statement executes after the assignment is made. A completely useless construct. Do not use it.

reg3 <= # 10 reg4 ;
next_statement;

The right hand side is evaluated at the current time, The next_statement executes after the evaluation of the RHS. The assignment to reg3 is put in a queue to be ex executed 10 time unites later.

Any delay in front of any statement might as well be thought of as an independent statement. so

#10 reg3 = reg4l;

behaves the same as

#10;
reg3 = reg4;


Continuous assignments using the assign keyword do not have transport delays. They use inertial delays. What this means is the delay on a continuous assignment cannot be longer than the switching delays on the RHS.
See the LRM section 10.3.3 Continuous assignment delays.