Verilog to VHDL translation

[Ponta]

Hello, can somebody please translate this verilog code to VHDL?
Thanks

module PWM(clock, switches, pwm
);

parameter sd=195;

input clock;
input [7:0] switches;

output pwm;
reg pwm;

reg [15:0] counter = 0;

always @ (posedge clock)
begin
counter = counter+1;
if(counter<=switches*sd) pwm = 1;
else pwm = 0;
if(counter>= 50_000) counter = 0;
end
endmodule

 

[ads-ee]

Do you know that the "counter <= switches*sd" in the if represents a large amount of logic? You're multiplying two 8-bit values and comparing the 16-bit result to a counter. Don't expect that to be super fast.

The code is also using blocking assignments, which is a bad coding practice in a edge triggered procedural block.

I also don't like the following code:

counter = counter+1;
if (counter>=50000) counter = 0;

I don't like to rely on the tools to interpret what I want, increment count, WAIT the count is 50000 or greater! clear the count instead!. I'd rather explicitly tell it what I want:

if (counter >= 50000) counter <= 0;
else counter <= counter +1;

which does the same thing, but leaves nothing to interpretation.

 

[FvM]

I wonder if you want to make the pwm period equal 50001 instead of 50000 clock cycles?

 

[ads-ee]

I figured nobody cares if they don't know how to count clocks, so I didn't bother to point that out. It seems like I'm always pointing that problem out.

- - - Updated - - -

BTW here is a translation.

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity PWM is
  generic
  (
    sd        : unsigned(7 downto 0) := X"C3" -- 195 in hex
  );
  port
  (
    clock     : in   std_logic;
    switches  : in   unsigned(7 downto 0);
    pwm       : out  std_logic
  );
end PWM;
 
architecture behave_PWM of PWM is
  signal counter : unsigned(15 downto 0);
 
begin -- architecture
  pwm_proc: process (clock)
  begin
    if (counter <= switches*sd) then
      pwm <= '1';
    else
      pwm <= '0';
    end if;
 
    if (counter >= 50000) then
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end process;
 
end behave_PWM;

---

It could have errors, but it does compile cleanly using Vivado's xvhdl.

 

[FvM]

I'm rather sure that the code has no errors. You can define sd also as an integer constant.

 

[Ponta]

Thank you for your answers. Can you tell me should this work when implemented on hardware? The task is to change brightness of LED's by switching 8 switches?
I don't have the board at home, and it's hard for me to go and check it at my university at this time.

 

[FvM]

should this work when implemented on hardware?

Yes. When I said no errors, I was talking about synthesis.