verilog to vhdl conversion?????

[me0414013]

while converting from verilog to VHDL which will be converted as signals which will be converted as variables????or
is it totally depend on the design????:?:

 

[dillikumar406]

in vhdl signals are the intermediate connections between the gates and modules. these signals are defined as wires in verilog

 

[me0414013]

thanks
what about registers, how to interpret that which will be converted as signals or variables????

 

[dillikumar406]

registers are nothing but wires but we use them in behavioral description only

 

[TrickyDicky]

Yes, its all about the behavioural description. Signals behave like non-block assignments in Verilog and Variables like blocking.
A signal can become a register, but so can a variable. It all depends on usage.