Verilog to detect double rising edge

[Rocketmagnet]

Looks good in general. If EDGE is asnychronous to clk, you should observe what's said about double registering. Otherwise, random errors can occur, either triggering of the output on first pulse or ignorance of input events.

Yes, EDGES is asynchronous to CLK. Can you explain more about what you mean by double registering?A google search for verilog double registering didn't seem to return any relevant results.

 

[j_andr]

always @(posedge CLK)
	edges_reg <= EDGES;

wire  pos_pulse =  EDGES & !edges_reg;

if your CLK edge is close to transition time of EDGES signal (what must
happen from time to time if the signals are asynchronous )
the 'pos_pulse' will be very short and 'not seen' by rest of your logic;

you should done something like this

edges_reg[0] <= EDGES
edges_reg[1] <= edges_reg[0];

pos_pulse = (edges_reg == 2'b01);

if your CLK is very fast ( >200-250MHz) you should have even
3 registers 'edges_reg'

J.A

 

[Rocketmagnet]

you should done something like this

edges_reg[0] <= EDGES
edges_reg[1] <= edges_reg[0];

pos_pulse = (edges_reg == 2'b01);

Got it. Right, makes sense. Thanks.