Verilog testbench for an 'image processing' task

samviva72 · Jun 13, 2011

I started learning verilog and FPGA a few weeks ago and I have used a verilog script that does a Sobel edge detection by running it on a video stream coming from a camera attached to my development board. The code worked fine as I can see the edges being picked up on the VGA display. I didn't simulate it before-hand because I found these verilog files online from another working project. But now I want to learn how to do it the proper way, i.e. simulate prior to testing on hardware. So following ModelSim tutorials, I reached upto the stage of 'Objects Window'.

Now as my input is an image of size 640 x 480, I don't think I can enter these 307,200 values one by one (unless I have a lot of time to waste). Could someone please guide me on how to write a testbench for my purpose? The header of my code is as follows:

Code:

module sobel_operator_eight_bit (clk, reset, data_in, data_en,data_out);

input    clk;
input	   reset;
input	   [7:0]	data_in;
input	   data_en;
output  [7:0]	data_out;

Is it possible to have the input data saved in a text file and then use some sort of 'read' command in the testbench? Or are any generic ways of simulating an image processing task in modelsim/verilog? I would appreciate any help, advice or code on how to achieve this.

Thanks.

gurucharapathy · Jun 13, 2011

You can use $readmemh() system function. Just google for details.

samviva72 · Jun 15, 2011

Thanks for the advice. I tried to write something as below that will read values from a text file containing hex values and write the output to another text file in decimal format. All the files compiled well in ModelSim. But when I click 'Start Simulation', nothing seems to happen. Can somebody please check my testbench first if it is any good before I go figure out what I am doing wrong in the Simulator software?

Thanks

Code:

module Sobel_testbench;

  reg clk_tb;
  reg reset_n_tb;
  reg in_valid_tb;
  reg  [7:0] in_data_tb;
  wire [7:0] out_data_tb;
  
  integer  i; // loop counter
  reg [7:0]  storage_values [0:153600]; // size of image 640 x 240
 
 // initalize the hexadecimal read from the txt file
 initial $readmemh("myhexval_1d.txt", storage_values);
 
 integer  fileOutput;

 
  // Control the clock signal
  initial
    clk_tb = 1'b0;
  always
    #5 clk_tb = ~clk_tb;
  
  initial
  begin
   
   reset_n_tb = 1'b1;
   #15 reset_n_tb = 1'b0;
	
	for (i=0; i < 153600; i=i+1)
	begin
	  in_data_tb = storage_values[i];

          fileOutput = $fopen("result_sobel.txt", "w");   
	  $fwrite(fileOutput,"%d\n",out_data_tb); 
	  $fclose(fileOutput); 
	end
  end
  
  //instatiate the test hardware block
  sobel_operator_eight_bit s1(clk_tb, reset_n_tb, in_valid_tb, in_data_tb, out_data_tb);
  

endmodule

Verilog testbench for an 'image processing' task

samviva72

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gurucharapathy

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samviva72

Newbie level 5

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Verilog testbench for an 'image processing' task

samviva72

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