Verilog Tesbench for FIFO Que Model

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ilucas86

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FIFO

Need help creating a testbench for given that include a series of write acesses with the folowing data: 0 x 0, 0x10, 0x20, 0x30, 0x40, and 0xff. In addition, the tesbench includes 7 consecutive read acesses to chek the following sequence of data: 0xff 0x40, 0x30, 0x20, 0x10, and 0x00.
 

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