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Verilog task similar to $signal_force

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amsverif

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Hi All,

I am creating a task in verilog that works similar to $signal_force verilog system task.
But with a lesser number of arguments i.e. - Signal to force, value to be forced and the time at which the value is to be forced.

As its not working for me I am working with 2 arguments - Signal to force, value to be forced.

My test case calls this task as
my_signal_force (Top.X1.X2.sig, 1'b0); // The signal can be bus also

Task definition -

task my_signal_force;
input reg [8*10:0] string;
input [31:0] val;

begin
$display("PRINT THE SIGNAL = %s \n", string);

force string = val;

$display("PRINT THE SIGNAL NOW= %s \n", string);
end
endtask


My main concern is if I take the first argument as wire and define as "input string;" . Verilog will not understand that the way I intend to as the signal is anyways a set of characters. So, I have to anyways take the first arg as string.
Now, how to force the signal with a value here ? How to get the signal forced in the force statement when I receive the left hand side as a string. The first display statement displays the signal path. But second doesn't diplay anything as it accepts the value 00000 ....
Can anyone help?
 

dave_59

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  • First of all, why don't you just use $signal_force without the optional arguments? Or put it inside your task?
  • Second, the force statement does not take a string. It uses the identifier that follows the force keyword to apply the force. In your example, string is the name of the variable that will be forced because that is the name if the identifier that follows the force keyword.
  • Third, Top.X1.X2.sig is not a string, it is a hierarchical reference to the signal sig. If you want a string literal, you need to put quotes around it. like "Top.X1.X2.sig".
  • Fourth, that string "Top.X1.X2.sig" in my third bullet is 13 character long and it wouldn't fit in the string input argument you declared, event if that's what you want to do.
  • Fifth, string is a reserved keyword in SystemVerilog, don't use it as an identifier.
 

amsverif

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Thanks Dave for your reply. I want my environment to be portable and hence don't want $signal_force which is tool dependant. Its $signal_force for Modelsim and nc_force for NCSim.
I have gone through some literature that the implementation I want to do is indeed possible but verilog can't do it standalone. It requires a PLI.
Please let me me know your comments on this.
 

dave_59

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Yes, PLI is the only way to look up Verilog identifiers by string names. Note that using the PLI to access signals this way can have a dramatic effect on performance of the simulation, since it prevents all sorts of optimizations. So you should think of another way to achieve what you want (and I don't know what you really want).
 

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