Verilog task query regarding while simulating

[verilog_vhdl7]

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Code Verilog - [expand]
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module xyz();
reg clk1;
reg [7:0] data_read;
reg [7:0] mem [0:7];
reg [3:0] rd_wr_addr;
reg rd;
 
task mem_rd;
  input  [3:0] addr;
  input clk;
  output [7:0] data;
  
  begin
    @ (posedge clk)
      rd = 1;
      rd_wr_addr = addr;
      
      
      @ (negedge clk)
        data = mem[rd_wr_addr];
        data_read = mem[rd_wr_addr];
        
        @ (posedge clk)
          rd = 0;
          rd_wr_addr = 0;
          
          end
          endtask
 
initial
begin
clk1 = 0;
reg [3:0] rd_wr_addr = 0;
reg rd = 0;
$readmemb("data.txt",mem);
mem_rd(4'b4,clk1,data_read);
end
 
always
#20 clk1 = ~ clk1;
 
endmodule

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hi...

This is a sample code of task read. I have a doubt here. I have mentioned a reg clk1 and used a task input called clk. Its compiling fine. but when i simulate in model sim this task is not taking clk1 but i can see my clk1 pulse.

Secondly if i remove the clk input from this task and trigger the task using clk1 its simulating fine.

Is it so that i cant use a clock input in my task and map it as i did using the above task.

i am getting my clk1 pulse ....then why is this task not taking this clk1 input.

thank you

 

[dave_59]

This is because in Verilog, task argument inputs are copied by value upon entry to the task, and task argument outputs are copied by value upon exit to the task. No updates occur through arguments during the task execution.

SystemVerilog has an argument pass by reference feature that gives you the behavior you are looking for. I don't know of synthesis tools support it, but most simulators support it.

 

[verilog_vhdl7]

Thank you. so that means i always have to use master clock which will update task output. Also does it mean that i cant use conditional statements using task input????

As delay is supported in task can i use non blocking statements in task???

or is there a rule also for task that i should be using specific kind of statements inside task i.e., blocking or non blocking as in case of functions mentioned in verilog IEEE reference guide(IEEE Std 1364-2001 clause 10.3.4)???

also i want to know the difference between
@(posedge) and
always @ (posedge) and
@(posedge);
// statements//;

why is it so in task i have to mention @ (posedge or negedge) instead of always @ (posedge or negedge).
because in a particular forum i read that @(posedge) is a delayed clock.

thank you

 

[TrickyDicky]

@(posedge a) is just a timing statement. Ie. wait until the next rising edge of a.

always @(posedge a) means the code here will be executed for every rising edge of a.

Hence why you cannot put an always in a task, as a task is meant to be called externally, not have code looping forever.

 

[verilog_vhdl7]

_____ ______ _______
| | | | | |
| | | | | |
____ | |_____| |______| |_______

for example this is my clock signal having three positive edges.
always @ (posedge a) ------- will it trigger at first positive edge??
@(posedge a) --------------- will it trigger at second positive edge??? (meaning of wait untill next rising edge)

suppose i have a clock pulse having three positive edges.
does it mean that if i use always @ posedge clk it will be triggered at first edge
and if i use @ (posedge clk) it will be delayed by one positive edge i.e., triggered at second edge???

thank you

 

[verilog_vhdl7]

ya i got it now after simulating. @ (posedge) is triggered only once.
Thank you all;

I have one more doubt

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Code Verilog - [expand]
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module test_timing();
reg d;
reg clk;
reg q;
 
initial 
begin
  clk = 0;
  d   = 0;
//end
 
@(posedge clk)
  q <= d;
  
  @(posedge clk)
  q <= d;
  
  @(posedge clk)
  q <= d;
  
  end
  
  always
   begin
   #20 clk = ~ clk;
    end
    
    always
     begin
       #45 d   = ~ d;
     end
  endmodule

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this is a test code i tested. Suppose i use blocking statements in @(posedge clk) it simulates correctly one after another and i get the desired results at every positive clock as 010.

but what if i use non blocking statements. The non blocking rule states that the rhs is updated first and after whole timing cycle the lhs is updated. Now i am using three non blocking statements for same output.

so when it encounters first @ (posedge clk) value d is updated
when it now encounters second @(posedge clk) a new value d is updated
when it encounters third another new value d should be updated

so the last one must be the output.

please correct me if i am wrong.

Thank you

 

[dave_59]

In your example, nothing reads "q" so there is no difference between blocking and non-blocking. It's only when one process reads, and another process writes the same variable synchronized to to same cycle that makes a difference. There is plenty of material out there on the internet about non-blocking assignments.

You may also want to read this for your earlier questions. See https://www.edaboard.com/threads/332596/#post1419672

 

[verilog_vhdl7]

thanks for your reply. one last doubt. there are three @ posedge statements.
so first q will be updated after first @ posedge??? and then second and so on.

because if i use always @ posedge clk then according to Non blocking rule all lhs will be updated after one clock cycle.

what i am trying to ask is when it encounters first @ the rhs will be updated and upon finishing of first posedge q will be updated and then it will go to second @ posedge.

also is @(posedge) updates immediately no matter if i use blocking or non blocking???

and what statements should i use in task..... blocking or non blocking????

thank you

 

[FvM]

All edge sensitive always blocks are scheduled in the same clock cycle, but the order is undefined.

Assigning the same variable in multiple always block throws a "multiple drivers" error in synthesis and makes no sense in simulation.

 

[verilog_vhdl7]

hi all

i need help understanding the following statement.

$monitor("%g",$time,,a,,b,,c,,d,,e,,f,,g,,bds,,,,bsd);

what is the use of %g???
i have mentioned only one format specifier and arguments are many....

thank you