Verilog task and fuction

[viresh128]

Hi, I am trying to learn task and function in verilog. Here's what i tried-
code-

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Code Verilog - [expand]
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module add_task(a,b,y, clk);
input [3:0] a, b;
output [4:0] y;
input clk;
reg[4:0] y;
 
 always @(posedge clk)
 begin 
 add(a,b,y);
 end
 
 task add;
  input [3:0] in1, in2;
  output [4:0] out;
  reg [4:0]out;
   begin 
   out<=in1+in2; 
   end
 endtask
 
endmodule

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and the TESTBENCH-

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Code Verilog - [expand]
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module tb_add_task;
 
    reg [3:0] a=0;
    reg [3:0] b=0;
    reg clk=0;
    wire [4:0] y;
    
    add_task uut (.a(a), .b(b), .y(y), .clk(clk));
   always #5 clk=~clk;
    
    always @(negedge clk) 
        begin
        a = $random;
        b = $random;
        end
endmodule

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THE PROBLEM IS THAT I AM GETTING A DELAYED OUTPUT, APPROX 10ns. COULD SOMEBODY PLS EXPLAIN WHY IS IT SO? FOR THE FIRST 15ns THE "Y" SIGNAL IS xxxx, ITS ONLY AFTER THIS THE ADDITION VALUES ARE BEING DISPLAYED. :sad::sad: PLEASE HELP.

 

[dave_59]

The problem with your task is that you are using a non-blocking assignment to assign the output argument, and then immediately leaving the task. The value of out has not been updated at that point, and it is the old value of out that gets copied to y. The next time you call the task, the value of out has been updated, and that it what gets copied out.

I suggest that you do not use a task unless it will consume time by having a delay control inside it (which renders it unsynthesizable for design by most tools)

 

[viresh128]

Thanks dave_59