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Verilog synthesis question

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eexuke

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Dear all,
Assume I have two descriptions:
1) assign a = (b==3'd5 && c==3'd6)? 1'b1:1'b0;
2) assign a = (b==3'd5 && c==3'd6);
If I am using DC to do synthesis,which expression will have a smaller gate count?

Many thanks in advance!
 

anjali

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actually the first one requires one extra mux to pass 1 or 0 to a.

i feel, but DC optimizes that mux because a = comparator output directly.
 

eexuke

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anjali said:
actually the first one requires one extra mux to pass 1 or 0 to a.

i feel, but DC optimizes that mux because a = comparator output directly.
So,you suggest use the 2) expression?
Thanks!
 

jelydonut

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I don't think it matters which you use as they should both synthesize to equivilant logic..

jelydonut
 

ami

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eexuke said:
Dear all,
Assume I have two descriptions:
1) assign a = (b==3'd5 && c==3'd6)? 1'b1:1'b0;
2) assign a = (b==3'd5 && c==3'd6);
If I am using DC to do synthesis,which expression will have a smaller gate count?

Many thanks in advance!
I just wonder that why dont you try to synthesize this code
Code:
module test(
            a,
            b,
            c
            );

input   [2:0]   b;
input   [2:0]   c;

output  a;


assign a = (b==3'd5 && c==3'd6); 
// assign a = (b==3'd5 && c==3'd6)? 1'b1:1'b0;
endmodule
and then check the result yourself :D
If you do that, you will find that DC will give the same result (with same constraint) in both of these cases. ( different library & condition will give different logic, but the result between 1 & 2 always the same)

Hope this help :D
[/img]
 

visualart

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The newer the version than the 2001.03, The result is the same.
But you'd better write it with the always statement.
Because the synospsys have defects to treat the assign statement
 

aravind

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Hi friends
but in 2004 and 2005 release i cant find assign state came in netlist.
i also tried RC (cadence).
no assign.

regards
aravind
 

kumar_eee

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In Leonardo-Spectrum


assign a = (b==3'd5 && c==3'd6);

*******************************************************

Cell: test View: INTERFACE Library: work

*******************************************************

Total accumulated area :
Number of Function Generators : 2
Number of IBUF : 6
Number of OBUF : 1
Number of gates : 2
Number of accumulated instances : 9
Number of ports : 7
Number of nets : 15
Number of instances : 9
Number of references to this view : 0


Cell Library References Total Area

IBUF xis3 6 x 1 6 IBUF
LUT3 xis3 1 x 1 1 Function Generators
LUT4 xis3 1 x 1 1 Function Generators
OBUF xis3 1 x 1 1 OBUF

Number of global buffers used: 0
***********************************************
Device Utilization for 3S50tq144
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 7 97 7.22%
Global Buffers 0 8 0.00%
Function Generators 2 1536 0.13%
CLB Slices 1 768 0.13%
Dffs or Latches 0 1827 0.00%
Block RAMs 0 4 0.00%
Block Multipliers 0 4 0.00%
Block Multiplier Dffs 0 144 0.00%

-----------------------------------------------
Using default wire table: STD




Slack Table at End Points


End points Slack Arrival Required
rise fall rise fall

a/ : n/a 8.54 8.54 n/a n/a



Critical Path Report

Critical path #1, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
c(2)/ 0.00 0.00 up 1.30
c_ibuf(2)/O IBUF 1.35 1.35 up 1.30
nx38/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #2, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
b(0)/ 0.00 0.00 up 1.30
b_ibuf(0)/O IBUF 1.35 1.35 up 1.30
nx38/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #3, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
b(1)/ 0.00 0.00 up 1.30
b_ibuf(1)/O IBUF 1.35 1.35 up 1.30
nx38/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #4, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
b(2)/ 0.00 0.00 up 1.30
b_ibuf(2)/O IBUF 1.35 1.35 up 1.30
nx38/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #5, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
c(0)/ 0.00 0.00 up 1.30
c_ibuf(0)/O IBUF 1.35 1.35 up 1.30
a_dup0/O LUT3 0.85 2.20 up 1.30
a_obuf/O OBUF 5.50 7.69 up 1.30
a/ 0.00 7.69 up 0.00
data arrival time 7.69

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 7.69
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #6, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
c(1)/ 0.00 0.00 up 1.30
c_ibuf(1)/O IBUF 1.35 1.35 up 1.30
a_dup0/O LUT3 0.85 2.20 up 1.30
a_obuf/O OBUF 5.50 7.69 up 1.30
a/ 0.00 7.69 up 0.00
data arrival time 7.69

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 7.69
----------
unconstrained path
------------------------------------------------------------------------------


assign a = (b==3'd5 && c==3'd6)? 1'b1:1'b0;


*******************************************************

Cell: test View: INTERFACE Library: work

*******************************************************

Total accumulated area :
Number of Function Generators : 2
Number of IBUF : 6
Number of OBUF : 1
Number of gates : 2
Number of accumulated instances : 9
Number of ports : 7
Number of nets : 15
Number of instances : 9
Number of references to this view : 0


Cell Library References Total Area

IBUF xis3 6 x 1 6 IBUF
LUT3 xis3 1 x 1 1 Function Generators
LUT4 xis3 1 x 1 1 Function Generators
OBUF xis3 1 x 1 1 OBUF

Number of global buffers used: 0
***********************************************
Device Utilization for 3S50tq144
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 7 97 7.22%
Global Buffers 0 8 0.00%
Function Generators 2 1536 0.13%
CLB Slices 1 768 0.13%
Dffs or Latches 0 1827 0.00%
Block RAMs 0 4 0.00%
Block Multipliers 0 4 0.00%
Block Multiplier Dffs 0 144 0.00%

-----------------------------------------------
Using default wire table: STD




Slack Table at End Points


End points Slack Arrival Required
rise fall rise fall

a/ : n/a 8.54 8.54 n/a n/a



Critical Path Report

Critical path #1, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
c(2)/ 0.00 0.00 up 1.30
c_ibuf(2)/O IBUF 1.35 1.35 up 1.30
nx44/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #2, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
b(0)/ 0.00 0.00 up 1.30
b_ibuf(0)/O IBUF 1.35 1.35 up 1.30
nx44/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #3, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
b(1)/ 0.00 0.00 up 1.30
b_ibuf(1)/O IBUF 1.35 1.35 up 1.30
nx44/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #4, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
b(2)/ 0.00 0.00 up 1.30
b_ibuf(2)/O IBUF 1.35 1.35 up 1.30
nx44/O LUT4 0.85 2.20 up 1.30
a_dup0/O LUT3 0.85 3.04 up 1.30
a_obuf/O OBUF 5.50 8.54 up 1.30
a/ 0.00 8.54 up 0.00
data arrival time 8.54

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 8.54
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #5, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
c(0)/ 0.00 0.00 up 1.30
c_ibuf(0)/O IBUF 1.35 1.35 up 1.30
a_dup0/O LUT3 0.85 2.20 up 1.30
a_obuf/O OBUF 5.50 7.69 up 1.30
a/ 0.00 7.69 up 0.00
data arrival time 7.69

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 7.69
----------
unconstrained path
------------------------------------------------------------------------------



Critical path #6, (unconstrained path)
NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
c(1)/ 0.00 0.00 up 1.30
c_ibuf(1)/O IBUF 1.35 1.35 up 1.30
a_dup0/O LUT3 0.85 2.20 up 1.30
a_obuf/O OBUF 5.50 7.69 up 1.30
a/ 0.00 7.69 up 0.00
data arrival time 7.69

data required time not specified
------------------------------------------------------------------------------
data required time not specified
data arrival time 7.69
----------
unconstrained path
------------------------------------------------------------------------------
 

anjali

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eexuke said:
anjali said:
actually the first one requires one extra mux to pass 1 or 0 to a.

i feel, but DC optimizes that mux because a = comparator output directly.
So,you suggest use the 2) expression?
Thanks!
both results same netlist with DC.
 

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