Verilog synchronous assign vs combinatorial assign

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Some Verilog questions :

1. Is "wire" used only for combinatorial logic and "reg" only for synchronous ?
2. The "assign" keyword together with the = operator is used only for "wire" while the <= operator is used only for "reg". correct ?
 

For an answer in correct Verilog terms, you should preferably refer to a text book or Verilog specifications.

The answer to both questions is "no".

The basic difference is between continuous assignments driving nets ("wire") and procedural assignments driving variables, e.g. reg, real and integer.

Procedural assignments can be both combinatorial and edge sensitive (synchronous) and use blocking "=" or non-blocking "<=" assignment operators.
 
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
when you say "procedural assignments" you mean assignments under "always" ?
 

See IEEE Std 1364:
6.2 Procedural assignments
Procedural assignments occur within procedures such as always, initial, task, and function.
Click to expand...
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…