`include "cypress.v"
module ParalelToSerial (
output Busy,
output Clkout,
output Dout,
input Clkin,
input [7:0] Din,
input En
);
reg busy;
reg dout;
reg clkout;
reg [3:0]cnt_spi;
always @ (posedge Clkin)
begin
if(En == 1'b1 && busy == 1'b0)
begin
clkout<=0; //should be checked
busy<=0;
if (cnt_spi < 7)
begin
Data <= {Data[6:0], 1'b0};
end
else if (cnt_spi == 7)
begin
Data <= Din;
end
cnt_spi = cnt_spi + 1;
end
if(cnt_spi==8)
begin
busy<=1'b1;
end
end
assign Busy = busy;
assign Dout = Data[7];
assign Clkout = clkout;
//`#end` -- edit above this line, do not edit this line
endmodule