Verilog Shift operations

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soloktanjung

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Hi friends,

Is this similar or not?

d=c2-[c3+(c3<<1)]>>3 and d=c2-[(c3<<3)+(c3<<1)]


I've read from a paper about the first one, but if I do as in the second one, is it still correct?

Is it the first one require less logic?

Anyone can help me?

Thanks in advances.
Hairo
 

You haven't shown what type of variables/signals those are, but the expressions don't look at all similar. Plug in some numbers and you'll see. Maybe you mistyped them?

By the way, you can't use square brackets in a Verilog expression.
 
Hi Echo47,

I've tested it with some numbers and both expression are not similar.

Thanks for the note that the square brackets can't be use in Verilog. I'll replace it with "(".

Thanks,
Hairo
 

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