Verilog Sensitivity List - posedge and level?

[forkconfig]

Can I have a sensitivity list for my always block as follows:

wire clk;
reg [100:0] myVector;
reg doStuff;

always @(posedge doStuff or myVector)

so that if any bits of myVector changes or if doStuff goes high the block executes.

 

[jrwebsterco]

I believe you can do that in Verilog simulators.
However, I doubt that any RTL synthesis tool would accept it without some kind of error or simulation mismatch warning, because it does not match any of the expected RTL templates for inferring sequential devices (latches or flops).