Oct 31, 2006 #1 K kma Newbie level 4 Joined Oct 16, 2006 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,308 prbs generator Can anyone tell me how to get the VERILOG RTL code for PRBS generator? Thanks.
Oct 31, 2006 #2 E echo47 Advanced Member level 6 Joined Apr 7, 2002 Messages 3,933 Helped 638 Reputation 1,274 Reaction score 90 Trophy points 1,328 Location USA Activity points 33,176 prbs verilog Here are the key lines of code for a 19-bit LFSR, which generates a PRBS. The output is simply lfsr bit 0. Code: reg [18:0] lfsr=0; always @ (posedge clock) lfsr <= {lfsr, ~lfsr[18]^lfsr[5]^lfsr[1]^lfsr[0]}; If you need a different cycle length, try this Xilinx app note: https://www.xilinx.com/bvdocs/appnotes/xapp210.pdf
prbs verilog Here are the key lines of code for a 19-bit LFSR, which generates a PRBS. The output is simply lfsr bit 0. Code: reg [18:0] lfsr=0; always @ (posedge clock) lfsr <= {lfsr, ~lfsr[18]^lfsr[5]^lfsr[1]^lfsr[0]}; If you need a different cycle length, try this Xilinx app note: https://www.xilinx.com/bvdocs/appnotes/xapp210.pdf