Verilog reg declaration

[FboDigit]

Hi all,

In verilog/systemverilog, is there a way to write in a reg'size with a variable ?

Example of what I want to do/say

integer i;
[B]reg [63:0] MyVar;[/B]
reg [3:0] EndVar

begin
for (i=0; i<10 ; i =i+1) begin  
    EndVar= MyVar[[B]((i*4)+3) : (i*4)[/B]];
...
...
...
end //for

the part I want to do is : EndVar= MyVar[((i*4)+3) : (i*4)];

I constantly get the error : # Error: VCP5116 fakefile.v : (3290, 46): Expected a constant as index: i*4+3.
and # Error: VCP5116 pci_exp_usrapp_tx.v : (3290, 46): Expected a constant as index: i*4.
with Aldec Actve-HDL 9.1

Please help me !! It is probably a small detail but i can't see it!

- - - Updated - - -

I have found my problem AND it was a small detail after all.
Declare the var "i" as parameter and everything is ok

But that brings me a new problem... the var "i" cannot be use in the for loop.

I could use two "i" variable,

parameter i_p =10;
integer i_r;

[B]reg [63:0] MyVar;[/B]
reg [3:0] EndVar

begin
i_r = i_p;
for (i_r=0; i_r<10 ; i_r =i_r+1) begin 
[B] i_p =i_r;[/B]   //THIS IS THE PROBLEMATIC LINE !!! (3283)
    EndVar= MyVar[[B]((i_p*4)+3) : (i_p*4)[/B]];
...
...
...
end //for

But the compiler say :# Error: VCP2858 fakefile.v : (3283, 25): i_p is not a valid left-hand side of a procedural assignment.

In a simple and direct question : Is there a wat to assign the value of a "parameter" to a "reg"

 

[fpgadsgnr]

Can you try following:

#################
integer i;
reg [63:0] MyVar;
reg [3:0] EndVar

begin
for (i=0; i<10 ; i =i+1) begin
EndVar= MyVar[i*4+3- :4];
...
...
...
end //for
#################

Let me know if it works.

Thanks,
Fpgadsgnr

 

[FvM]

Variable part select, as sugested will work

EndVar= MyVar[i*4+3- :4];

A more generic method will use nested for loops:

for (i=0; i<10 ; i=i+1) 
begin 
  for (j=0; j<4 ; j=j+1)
    EndVar[j]= MyVar[i*4+j];
  ...
end

 

[FboDigit]

Can you try following:

#################
integer i;
reg [63:0] MyVar;
reg [3:0] EndVar

begin
for (i=0; i<10 ; i =i+1) begin
EndVar= MyVar[i*4+3- :4];
...
...
...
end //for
#################

Let me know if it works.

Thanks,
Fpgadsgnr

Hi Fpgadsgnr!

It compiled !!! but there is 2 thing I want to know.

The first is that the right part of the asignation don't have the i*4 and this is kind of important in my loop.
The second is : What the " - " is used for ??? I really don't understant the meaning of this operator in this circumstance.

I am not sure it will work but so far it is compiling and this is a big must !!!!

EDIT : Nevermind I understand now the use of "part-select" and I must say that this is very usefull. Thanks !!!!!!

 

[FvM]

Review IEEE Std 1364, Chapter 5.2.1 Vector bit-select and part-select addressing, or an explanation in your favorite Verilog text book.

 

[FboDigit]

It is working like a charm thanks a lot !!!