vcnvcc
Full Member level 2
Hello friends,
I have signal called signal - reg [7:0]signal_A, now i want this signal to be in integer form.
like this
integer signal_A_converted[256:0];
and I eventually I need -
signal_a1 = signal_A_converted[256:128]; // basically I need reg to integer conversion in parts..
signal_a2 = signal_A_converted[127:0];
I have tried different methods and checked, but I am not finding the correct method. could you please help.
(stackoverflow.com/questions/5666456/converting-a-wire-value-to-an-integer-in-verilog - gives me error)
I have signal called signal - reg [7:0]signal_A, now i want this signal to be in integer form.
like this
integer signal_A_converted[256:0];
and I eventually I need -
signal_a1 = signal_A_converted[256:128]; // basically I need reg to integer conversion in parts..
signal_a2 = signal_A_converted[127:0];
I have tried different methods and checked, but I am not finding the correct method. could you please help.
(stackoverflow.com/questions/5666456/converting-a-wire-value-to-an-integer-in-verilog - gives me error)
