davyzhu
Advanced Member level 1
psl vs systemverilog
Hi all,
I am a Verilog user.
I want to use assertion based verification in my project. And I found OVL(Open Verification library).
Do you think which one of the OVL is better? Verilog, PSL or SystemVerilog?
And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in SystemVerilog again?
Best regards,
Davy
Hi all,
I am a Verilog user.
I want to use assertion based verification in my project. And I found OVL(Open Verification library).
Do you think which one of the OVL is better? Verilog, PSL or SystemVerilog?
And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in SystemVerilog again?
Best regards,
Davy