verilog-problem write text file

out_x[0]    out_y[0]       out_z[0]
out_x[1]    out_y[1]       out_z[1]
out_x[2]    out_y[2]       out_z[2]
.                  .                   .
.                  .                   .
.                  .                   .
.                  .                   .
out_x[n]     out_y[n]       out_z[n]

`define Lenght_v 22
integer file,stat,i,j,m,n,k,out;
integer file_v,stat_v;
real out_x[0:`Lenght_v-1];
real out_y[0:`Lenght_v-1];
real out_z[0:`Lenght_v-1];
output reg clk;
always@(posedge clk)
	begin 
		out=$fopen("out.txt","w");
		for(k=0;k<`Lenght_v;k=k+1)
			begin
				$fwrite (out,"a=%f\n b=%f\n c=%f\n",out_x[k],out_y[k],out_z[k]); 
				
			end 
			$fflush(out);
	end

out_x[0]
out_y[0]
out_z[0]
out_x[1]
out_y[1]
out_z[1]
.
.
.

$fwrite (out,"a=%f     b=%f     c=%f\n",out_x[k],out_y[k],out_z[k]);